Altera Stratix V Avalon-ST - Manual (Page 115)

Figure 5-41: Hard IP Reconfiguration Bus Timing of Read-Only Registers
avmm_clk
hip_reconfig_rst_n
user_mode
ser_shift_load
interface_sel
avmm_wr
avmm_wrdata[15:0]
avmm_rd
avmm_rdata[15:0]
D0
D0
D1
D1
D2 D3
324 ns 4 clks
4 clks
4 clks
For a detailed description of the Avalon-MM protocol, refer to the Avalon Memory Mapped Interfaces
chapter in the Avalon Interface Specifications.
Related Information
• Avalon Interface Specifications
• PCI SIG Gen2 x8 Merged Design - Stratix V
Power Management Signals
Table 5-21: Power Management Signals
Signal Direction Description
pme_to_cr Input Power management turn off control register.
Root Port—When this signal is asserted, the Root Port sends the
PME_turn_off
message.
Endpoint—This signal is asserted to acknowledge the
PME_turn_
off
message by sending
pme_to_ack
to the Root Port.
UG-01097_avst
2014.12.15
Power Management Signals 5-63
Interfaces and Signal Descriptions Altera Corporation
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