Altera Stratix V Avalon-ST User Manual
Page 32
The preceding timing diagram illustrates the following sequence of events:
1. The Application Layer indicates it is ready to receive requests by asserting
RxSTReady_o
. The RX
Avalon-ST interface initiates a Configuration Read, asserting its
RxStSop_i
and
RxStValid_i
signals.
2. At the falling edge of
RxStSop_i
, the Avalon-MM master interface asserts
cfg_rden_o
and specifies
the address on
cfg_addr_o[31:0]
.
3. The Function 0 Avalon-MM slave interface asserts
cfg_rddavalid_i
and drives the data on
cfg_rddata_i[31:0]
.
4. On the falling edge of
cfg_rddavalid_i
, the TX interface asserts
TxStSop_o
and
TxStValid_o
and
drives the data of
TxStData_o[255:0]
. This is the Completion Request to the host corresponding to
its Configuration Read Request.
Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface
The following timing diagram illustrates a configuration write to Function 0 starting at time 61859 ns in
the simulation.
The timing diagram illustrates the following sequence of events:
1. The Application Layer indicates it is ready to receive requests by asserting
RxSTReady_o
. The RX
Avalon-ST interface initiates a Configuration Write, asserting its
RxStSop_i
and
RxStValid_i
signals.
2. At the falling edge of
RxStSop_i
, the Avalon-MM master interface asserts
cfg_wren_o
and specifies
the data on
cfg_wrdata_o[31:0]
. The Master interface also assert
cfg_writeresponserequest_o
, to
request completion status from Function 0.
3. On the falling edge of
cfg_writeresponserequest_o
, Function 0 asserts
cfg_writeresponse-
valid_i
.
4. On the falling edge of
cfg_writeresponsevalid_i
, the TX interface asserts
TxStSop_o
and
TxStValid_o
and drives the completion data on
TxStData_o[255:0]
.
3-8
Timing for Configuration Write to Function 0 for the 256-Bit Avalon-ST Interface
UG-01097_avst
2014.08.18
Altera Corporation
Getting Started with the Configuration Space Bypass Mode Qsys Example Design