Altera Stratix V Avalon-ST - Manual (Page 61)

Figure 5-4: 64-Bit Avalon-ST rx_st_data Cycle Definition for 3-Dword Header TLPs with Qword
Aligned Address
In the following figure,
rx_st_be[7:4]
corresponds to
rx_st_data[63:32]
.
rx_st_be[3:0]
corresponds to
rx_st_data[31:0]
.
clk
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_be[7:4]
rx_st_be[3:0]
Header 1 Data1 Data3
Header 0 Header2 Data0 Data2
F 1
F E
Figure 5-5: 64-Bit Avalon-ST rx_st_data Cycle Definitions for 4-Dword Header TLPs with Qword
Aligned Addresses
The following figure shows the mapping of Avalon-ST RX packets to PCI Express TLPs for TLPs for a
four dword header with qword aligned addresses with a 64-bit bus.
pld_clk
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_be[7:4]
rx_st_be[3:0]
header1 header3 data1
header0 header2 data0
F
F
UG-01097_avst
2014.12.15
Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface 5-9
Interfaces and Signal Descriptions Altera Corporation
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