Altera Stratix V Avalon-ST User Manual
Page 21
10.From the Simulation list, select ModelSim
®
. From the Format list, select the HDL language you
intend to use for simulation.
11.Click Next to display the Summary page.
12.Check the Summary page to ensure that you have entered all the information correctly.
13.Click Finish to create the Quartus II project.
14.Before compiling, you must assign I/O standards to the pins of the device. Refer to Making Pin
Assignments to Assign I/O Standard to Serial Data Pins for instructions.
15.You must connect the
pin_perst
reset signal to the correcsponding
nPERST
pin of the device. Refer to
the definition of
pin_perst
in the Reset, Status, and Link Training Signals section for more informa‐
tion.
16.Next, set the value of the
test_in
bus to a value that is compatible for hardware testing. In Qsys design
example provided,
test_in
is a top-level port.
a. Comment out the
test_in
port in the top-level Verilog generated file.
b. Add the following declaration,
wire[31:0] test_in
, to the same top-level Verilog file.
c. Assign
hip_ctrl_test_in = 32'hA8
.
d. Connect
test_in
to
hip_ctrl_test_in
.
Refer to the definition of
test_in
in the Test Signals section for more information about the bits of the
test_in
bus.
17.Add the Synopsys Design Constraint (SDC) shown in the following example below to the top-level
design file for your Quartus II project.
18.To compile your design using the Quartus II software, on the Processing menu, click Start Compila‐
tion. The Quartus II software then performs all the steps necessary to compile your design.
Example 2-1: Synopsys Design Constraints
create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*}
derive_pll_clocks
derive_clock_uncertainty
# PHY IP reconfig controller constraints
# Set reconfig_xcvr clock
# Modify to match the actual clock pin name
# used for this clock, and also changed to have the correct period set
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}{*reconfig_xcvr_clk*}
# HIP Soft reset controller SDC constraints
set_false_path -to [get_registers* altpcie_rs_serdes|fifo_err_sync_r[0]]
set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to[get_registers
*altpcie_rs_serdes|*]
# Hard IP testin pins SDC constraints
set_false_path -from [get_pins -compatibilitly_mode *hip_ctrl*]
UG-01097_avst
2014.12.15
Compiling the Design in the Qsys Design Flow
2-7
Getting Started with the Stratix V Hard IP for PCI Express
Altera Corporation