Altera Stratix V Avalon-ST - Manual (Page 286)

Additional Information
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2014.12.15
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Revision History for the Avalon-St Interface
Date Version Changes Made
2014.12.15 14.1 Made the following changes to the user guide:
• Added simulation log file,
altpcie_monitor__dlhip_tlp_file_
log.log in your simulation directory. Generation of the log file
requires the following simulation file, altera/altera_pcie/
altera_pcie_a10_hip/altpcie_monitor_a10_dlhip_sim.sv , that was not
present in earlier releases of the Quartus II software.
• Added statement that the bottom left hard IP block includes the
CvP functionality for flip chip packages. For other package types,
the CvP functionality is in the bottom right block.
• Corrected bit definitions for
CvP Status
register.
• Updated definition of
CVP_NUMCLKS
in the
CvP Mode Control
register.
• Added definitions for
test_in[2]
,
test_in[6]
and
test_in[7]
.
• Added 2 additional SDC timing constraints for Gen3 in SDC
Timing Constraints Required for the Stratix V Hard IP for PCIe
and Design Example.
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