Altera Stratix V Avalon-ST - Manual (Page 197)

counter. Essentially, this means the data sink knows the data source has less than a full
MAX_PAYLOAD
worth of credits, and therefore is starving.
b. When an internal timer expires from the time the last FC Update DLLP was sent, which is
configured to 30 µs to meet the PCI Express Base Specification for resending FC Update DLLPs.
c. When the
credit allocated
counter minus the last sent
credit allocated
counter is greater than
or equal to 25% of the total credits available in the RX buffer, then the FC Update DLLP request is
raised to high priority.
After arbitrating, the FC Update DLLP that won the arbitration to be the next item is transmitted.
In the worst case, the FC Update DLLP may need to wait for a maximum sized TLP that is currently
being transmitted to complete before it can be sent.
7. The original write requester receives the FC Update DLLP. The
credit limit
value is updated. If
packets are stalled waiting for credits, they can now be transmitted.
Note: You must keep track of the credits consumed by the Application Layer.
Throughput of Posted Writes
The throughput of posted writes is limited primarily by the Flow Control Update loop as shown in Figure
12-1 . If the write requester sources the data as quickly as possible, and the completer consumes the data as
quickly as possible, then the Flow Control Update loop may be the biggest determining factor in write
throughput, after the actual bandwidth of the link.
The figure below shows the main components of the Flow Control Update loop with two communicating
PCI Express ports:
• Write Requester
• Write Completer
To allow the write requester to transmit packets continuously, the
credit allocated
and the
credit
limit
counters must be initialized with sufficient credits to allow multiple TLPs to be transmitted while
waiting for the FC Update DLLP that corresponds to the freeing of credits from the very first TLP
transmitted.
You can use the RX Buffer space allocation - Desired performance for received requests to configure
the RX buffer with enough space to meet the credit requirements of your system.
Related Information
PCI Express Base Specification 2.1 or 3.0
Throughput of Non-Posted Reads
To support a high throughput for read data, you must analyze the overall delay from the time the Applica‐
tion Layer issues the read request until all of the completion data is returned. The Application Layer must
be able to issue enough read requests, and the read completer must be capable of processing these read
requests quickly enough (or at least offering enough non-posted header credits) to cover this delay.
However, much of the delay encountered in this loop is well outside the IP core and is very difficult to
estimate. PCI Express switches can be inserted in this loop, which makes determining a bound on the
delay more difficult.
UG-01097_avst
2014.12.15
Throughput of Posted Writes 12-3
Throughput Optimization Altera Corporation
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