Files Generated for Altera IP Cores
Figure 2-3: IP Core Generated Files
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
_bb.v - Verilog HDL black box EDA synthesis file
_inst.v or .vhd - Sample instantiation template
synthesis - IP synthesis files
.qip - Lists files for synthesis
testbench - Simulation testbench files
1
- Testbench for supported simulators
.v or .vhd - Top-level IP variation synthesis file
simulation - IP simulation files
.sip - NativeLink simulation integration file
- Simulator setup scripts
- IP core variation files
.qip or .qsys - System or IP integration file
_generation.rpt - IP generation report
.bsf - Block symbol schematic file
.ppf - XML I/O pin information file
.spd - Combines individual simulation startup scripts
1
.html - Contains memory map
.sopcinfo - Software tool-chain integration file
_syn.v or .vhd - Timing & resource estimation netlist 1
.debuginfo - Lists files for synthesis
.v, .vhd, .vo, .vho - HDL or IPFS models
2
_tb - Testbench for supported simulators
_tb.v or .vhd - Top-level HDL testbench file
Related Information
•
Simulating the Example Design
on page 3-5
•
Generating the Testbench
on page 2-3
•
Simulating the Example Design
on page 3-5
•
Simulating the Example Design
on page 3-5
2-8
Compiling the Design in the Qsys Design Flow
UG-01097_avst
2014.12.15
Altera Corporation
Getting Started with the Stratix V Hard IP for PCI Express
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