Altera Stratix V Avalon-ST - Manual (Page 2)

Datasheet
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2014.12.15
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Stratix V Avalon-ST Interface for PCIe Datasheet
Altera ® Stratix ® V FPGAs include a configurable, hardened protocol stack for PCI Express ® that is
compliant with PCI Express Base Specification 2.1 or 3.0. The Hard IP for PCI Express using the Avalon
Streaming (Avalon-ST) interface is the most flexible variant. However, this variant requires a thorough
understanding of the PCIe ® Protocol.
Figure 1-1: Stratix V PCIe Variant with Avalon-ST Interface
Application
Layer
(User Logic)
Avalon-ST
Interface PCIe Hard IP
Block
PIPE
Interface PHY IP Core
for PCIe
(PCS/PMA)
Serial Data
Transmission
Table 1-1: PCI Express Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4,
and 8 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers
double for duplex operation. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per
second for Gen2, and 8.0 giga-transfers per second for Gen3. Gen1 and Gen2 use 8B/10B encoding which
introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to
encoding to less than 1%.
Link Width
×1 ×2 ×4 ×8
PCI Express Gen1
(2.5 Gbps)
2 4 8 16
PCI Express Gen2
(5.0 Gbps)
4 8 16 32
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