Altera Stratix V Avalon-ST - Manual (Page 175)

Figure 10-3: Configuration Space Bypass Mode
Custom
Configuration
Space
RX Buffer &
Flow Control
Configuration
Space
(Disabled)
Avalon-ST RX
Transaction Layer
Data Link
PHY Interface
Transaction Layer
Hard IP for PCI Express Application Layer
(Soft Logic)
Altera FPGA
Data Link Layer Physical Layer
Avalon-ST TX
In Configuration Space Bypass Mode, the hard IP passes all well-formed TLPs to the Application Layer
using the Avalon-ST RX interface. The hard IP detects and drops malformed TLPs. Application Layer
logic must detect and handle Unsupported Requests and Unexpected Completions. Application Layer
logic must also generate all completions and messages and transmit them using the Avalon-ST TX
interface. Refer to “Configuration Space Bypass Mode Input Signals” on page 8–42 and “Configuration
Space Bypass Mode Output Signals” on page 8–44 for descriptions of these signals.
In Configuration Space Bypass Mode, the Power Management, MSI and legacy interrupts, Completion
Errors, and Configuration Interfaces are disabled inside the hard IP. You must implement these features
in the Application Layer. You can use the LMI bus in Configuration Space Bypass mode to log the TLP
header of the first error in the AER registers.
Related Information
Configuration Space Bypass Mode Interface Signals on page 5-44
Error Checking and Handling in Configuration Space Bypass Mode
In Configuration Space Bypass mode, the Application Layer receives all TLPs that are not malformed. The
Transaction Layer detects and drops malformed TLPs. Refer to “Errors Detected by the Transaction
Layer” on page 15–3 for the malformed TLPs the Transaction Layer detects. The Transaction Layer also
detects Internal Errors and Corrected Errors. Real-time error status signals report Internal Errors and
Correctable Errors to the Application Layer. The Transaction Layer also records these errors in the AER
registers. You can access the AER registers using the LMI interface.
Because the AER header log is not available in Configuration Space Bypass Mode, the Application Layer
must implement logic to read the AER header log using the LMI interface. You may need to arbitrate
between Configuration Space Requests to the AER registers of the Hard IP for PCI Express and Configu‐
ration Space Requests to your own Configuration Space. Or, you can avoid arbitration logic by deasserting
the
ready
signal until each LMI access completes.
10-8 Error Checking and Handling in Configuration Space Bypass Mode
UG-01097_avst
2014.08.18
Altera Corporation IP Core Architecture
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