Maxim Integrated MAXQ622 - Manual (Page 96)

MAXQ612/MAXQ622 User’s Guide
Maxim Integrated 5-23
REGISTER DESCRIPTION
PR1 (0Ah, 03h) Phase Register 1
Initialization: The phase register is cleared to 0000h on all forms of reset .
Read/Write Access: Unrestricted read/write .
PR1.15 to PR1.0 Phase Register 1 Bits 15:0. This register is used to load and read the 16-bit value in the
phase register that determines the baud rate for the serial port 1 .
SMD1 (0Bh, 03h) Serial Port Mode Register 1
Initialization: This register is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
SMD1.0 (FEDE1) Framing Error-Detection Enable. This bit selects the function of SM0 (SCON1 .7):
FEDE = 0: SCON1 .7 functions as SM0 for serial port mode selection .
FEDE = 1: SCON1 .7 is converted to the framing error (FE) flag .
SMD1.1 (SMOD1) Serial Port 1 Baud-Rate Select . The SMOD selects the final baud rate for the asynchronous
mode:
SMOD = 1: 16 times the baud clock for mode 1 and 3, 32 times the system clock for mode 2 .
SMOD = 0: 64 times the baud clock for mode 1 and 3, 64 times the system clock for mode 2 .
SMD1.2 (ESI1) Enable Serial Port 1 Interrupt. Setting this bit to 1 enables interrupt requests generated by
the RI or TI flags in SCON1 . Clearing this bit to 0 disables the serial port interrupt .
SMD1.7 to SMD1.3 Reserved, read returns 0.
SPICF0 (0Ch, 03h) SPI Configuration Register 0
Initialization: This buffer is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
SPICF0.0 (CKPOL) Clock Polarity Select. This bit is used with the CKPHA bit to determine the SPI transfer
format . When the CKPOL is set to 1, the SPI uses the clock falling edge as an active edge .
When the CKPOL is cleared to 0, the SPI selects the clock rising edge as an active edge .
SPICF0.1 (CKPHA) Clock Phase Select . This bit is used with the CKPOL bit to determine the SPI transfer
format . When the CKPHA is set to 1, the SPI samples input data at an inactive edge . When
the CKPHA is cleared to 0, the SPI samples input data at an active edge .
SPICF0.2 (CHR) Character Length Bit. The CHR bit determines the character length for an SPI transfer
cycle . A character can consist 8 or 16 bits in length . When CHR bit is 0, the character is 8
bits; when CHR is set to 1, the character is 16 bits .
SPICF0.5 to SPICF0.3 Reserved . Reads return 0 .
SPICF0.6 (SAS) Slave Active Select. This bit is used to determine the SSEL active state . When the SAS is
cleared to 0, the SSEL is active low and responds to an external low signal . When the SAS
is set to 1, the SSEL is active high .
SPICF0.7 (ESPII) SPI Interrupt Enable . Setting this bit to 1 enables the SPI interrupt when MODF, WCOL,
ROVR, or SPIC flags are set . Clearing this bit to 0 disables the SPI interrupt .
SPICK0 (0Dh, 03h) SPI Clock Register 0
Initialization: This buffer is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
SPICK0.7 to SPICK0.0 (CKR[7:0]) Clock-Divide Ratio Bits 7:0. These bits select one of the 256 divide ratios (0 to 255) used
for the baud-rate generator, with bit 7 as the most significant bit . The frequency of the SPI
baud rate is calculated using the following equation:
SPI Baud Rate = 0 .5 x System Clock/(divide ratio + 1)
This register has no function when operating in slave mode and the clock generation
circuitry should be disabled .