Maxim Integrated MAXQ622 - Manual (Page 91)

MAXQ612/MAXQ622 User’s Guide
5-18 Maxim Integrated
REGISTER DESCRIPTION
TB0C (08h, 02h) Timer B0 Compare Register (16-bit register)
Initialization: This register is cleared to 0000h on all forms of reset .
Read/Write Access: Unrestricted read/write .
TB0C.15 to TB0C.0 Timer B0 Compare Bits 15:0. This register is used for comparison versus the TBV value
when Timer B is operated in compare mode .
TB0V (09h, 02h) Timer B0 Value Register (16-bit register)
Initialization: The Timer B0 Value is cleared to 0000h on all forms of reset .
Read/Write Access: Unrestricted read/write .
TB0V.15 to TB0V.0 Timer B0 Value Bits 15:0. This register is used to load and read the 16-bit Timer B value .
TB1C (0Ah, 02h) Timer B1 Compare Register (see the TB0C register bit description)
TB1V (0Bh, 02h) Timer B1 Value Register (see the TB0V register bit description)
IRV (0Ch, 02h) IR Value Register (16-bit register)
Initialization: This register is cleared to 0000h on all forms of reset .
Read/Write Access: Unrestricted read/write .
IRV.15 to IRV.0 IR Value Register Bits 15:0. The IRV register is a 16-bit register that holds the current
IR timer value . The IR timer value starts counting when the IREN bit is set to 1 . It stops
counting when the IREN bit is cleared to 0 and retains the current timer value .
SCON0 (00h, 03h) Serial Port 0 Control Register
Initialization: The serial port control is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
SCON0.0 (RI) Receive Interrupt Flag. This bit indicates that a data byte has been received in the serial
port buffer . The bit is set at the end of the 8th bit for mode 0, after the last sample of the
incoming stop bit for mode 1 subject to the value of the SM2 bit, or after the last sample of
RB8 for modes 2 and 3 . This bit must be cleared by software once set .
SCON0.1 (TI) Transmit Interrupt Flag. This bit indicates that the data in the serial port data buffer has
been completely shifted out . It is set at the end of the last data bit for all modes of operation
and must be cleared by software once set .
SCON0.2 (RB8) 9th Received Bit State. This bit identifies the state of the 9th bit of received data in serial
port modes 2 and 3 . When SM2 is 0, it is the state of the stop bit in mode 1 . This bit has no
meaning in mode 0 .
SCON0.3 (TB8) 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial
port modes 2 and 3 .
SCON0.4 (REN) Receive Enable .
REN_0 = 0: Serial port 0 receiver disabled .
REN_0 = 1: Serial port 0 receiver enabled for modes 1, 2, and 3 . Initiate synchronous
reception for mode 0 .
SCON0.5 (SM2) Serial Port Mode Bit 2. Setting this bit in mode 1 ignores reception if an invalid stop
bit is detected . Setting this bit in mode 2 or 3 enables multiprocessor communications,
and prevents the RI bit from being set and the interrupt from being asserted if the 9th bit
received is 0 . This bit also used to support mode 0 for clock selection:
SM2 = 0: Clock is divided by 12 .
SM2 = 1: Clock is divided by 4 .