Maxim Integrated MAXQ622 - Manual (Page 22)

MAXQ612/MAXQ622 User’s Guide
2-18 Maxim Integrated
• A system library function that checks arguments before raising the privilege level must do so in an atomic fash-
ion using PRIVT0 and PRIVT1 to prevent short-circuiting the check (the rule about disabling interrupts also applies).
Example:
system_library:
move IGE, #0
move PRIVT0, #HIGH
… ; check
jump ne, exit move PRIVT1, #HIGH
; … action
exit:
move PRIV, #LOW
move IGE, #1
ret
2.6.2 Privilege Exception Interrupt
Any attempt to exceed the current privilege level causes a privilege exception interrupt that can be handled by system
code . Examples that cause an interrupt are writing high to PRIV from user code, or trying to read system code while
PRIV is low . The intent of the interrupt is to notify low priority code when an operation was denied by hardware .
2.6.3 Memory Access Protection Impact on Data Pointers (and Code Pointer)
Memory access protection complicates the use of the data and code pointers . In the MAXQ architecture, code pointers
must be activated before use in order for memory data to be available on the same cycle it is needed using synchro-
nous RAMs . This means that data is essentially prefetched into the physical data pointer when the pointer is activated
(e .g ., by loading an address to DP[0]) . This can have some unintended consequences with respect to the memory
protection function .
Specifically, when MPE is enabled, and when executing from RAM, any write to the traditional MAXQ data pointers,
DP[0], DP[1], and BP, OFFS, or DPC, has the potential to generate a memory fault .
For example, a scenario in which code is executed from RAM is presented . In this particular case, the code is stored in
a serial EEPROM . The code is loaded dynamically into RAM when needed . It is assumed this code has to have access
to RAM variables, and remember we are executing from RAM .
To accomplish this without memory access protection, the customer would configure DPC and load DP[0] and then
call the utility ROM function UROM_moveDP0 . The code would look like the following:
MOVE DPC, #REQUIRED_DP0_MODE
; (1)
MOVE DP[0], #REQUESTED_RAM_ADDRESS ; (2)
LCALL UROM_MOVEDP0
; (3)
; actual ROM function
MOVE DP[0], DP[0] ; (3a)
MOVE GR, @DP[0] ; (3b)
RET ; (3c)
In the above example, (1) and (2) are both considered valid pointer activation instructions . In the MAXQ transfer-
triggered architecture every standard instruction represents a MOVE from a source (SRC) to a destination (DST) . The
POP ACC instruction is equivalent to MOVE ACC, @SP--, JUMP LABEL is equivalent to MOVE IP, #LABEL, and so on .
With the exception of a handful of arithmetic and logical instructions, every instruction is interpreted as a MOVE DST,
SRC operation .