Maxim Integrated MAXQ622 - Manual (Page 178)

MAXQ612/MAXQ622 User’s Guide
12-8 Maxim Integrated
Bit 6: VBUS Detect (VBUS). This bit is set when the VBUSDET signal has made a 0-to-1 transition (VBUS is present) .
This bit remains set unless cleared by software, a USB controller reset, or a USB bus reset . Setting this bit to 1 causes
an interrupt to the CPU if USB VBUS detect interrupt is enabled (VBUSIE = 1) .
Bit 5: No VBUS (NOVBUS). The SIE sets this bit when the VBUSDET signal has made a 1-to-0 transition (VBUS is not
present) . This bit remains set unless cleared by software, a USB controller reset or a USB bus reset . Setting this bit to
1 causes an interrupt to the CPU if USB no VBUS interrupt is enabled (NOVBUSIE = 1) .
Bit 4: Suspend (SUSP). The SIE sets this bit to 1 after 3ms of idle state on the bus . This bit remains set unless cleared
by software, a USB controller reset, or a USB bus reset . Setting this bit to 1 causes an interrupt to the CPU if USB bus
suspend interrupt is enabled (SUSPIE = 1) .
Bit 3: USB Bus Reset (BRST). The BRST bit is set to 1 when a USB bus reset has been detected by the SIE logic .
When this bit is set to 1, the USB controller resets its internal registers to their default values . This bit is self-cleared by
hardware at the end of USB bus reset condition . The bit can also be cleared by software writing a 0 . Setting this bit to
1 causes an interrupt to the CPU if USB bus reset interrupt is enabled (BRSTIE = 1) .
Bit 2: USB Bus Active (BACT). The bit indicates whether there is any USB bus activity . This bit is set to 1 if the USB
controller receives a SYNC field, and reset after 32 bit times of J-state or during a USB bus reset . This bit can be
cleared by software writing a 0 . Setting this bit to 1 causes an interrupt to the CPU if USB bus active interrupt is enabled
(BACTIE = 1) .
Bit 1: Remote Wake-Up Signaling Done (RWUDN). The SIE sets this bit to 1 at the end of remote wake-up signaling
(10ms of K-state) . This bit remains set unless cleared by software, a USB controller reset, or a USB bus reset . Setting
this bit to 1 causes an interrupt to the CPU if USB remote wake-up signaling done interrupt is enabled (RWUDNIE = 1) .
Bit 0: D+ Activity (DPACT). The SIE sets this bit to 1 when activity is detected on the D+ pin . Setting this bit to 1 causes
an interrupt to the CPU if D+ activity interrupt is enabled (DPACTIE = 1) .
12.4.6 Endpoint Interrupt Enable Register (EPIEN)
Note: This register is only accessible when USBEN = 1 .
All bits in this register have a self-clearing mechanism that clears the interrupt enable when a bus reset condition is
detected .
Bits 7 and 6: Reserved. Reads returns zero.
Bit 5: Setup Data Available Interrupt Enable (SUDAVIE). Setting this bit to 1 causes an interrupt to the CPU when the
setup data is available (SUDAV = 1) . Clearing this bit to 0 disables the data ready interrupt from generating .
Bit 4: EP3 IN Buffer Available Interrupt Enable (IN3BAVIE). Setting this bit to 1 causes an interrupt to the CPU when
the EP3-IN buffer is available (IN3BAV = 1) . Clearing this bit to 0 disables the buffer ready interrupt from generating .
Bit 3: EP2-IN Buffer Available Interrupt Enable (IN2BAVIE). Setting this bit to 1 causes an interrupt to the CPU when
the EP2-IN buffer is available (IN2BAV = 1) . Clearing this bit to 0 disables the buffer ready interrupt from generating .
Bit 2: EP1-OUT Data Available Interrupt Enable (OUT1DAVIE). Setting this bit to 1 causes an interrupt to the CPU when
the EP1-OUT data is available (OUT1DAV = 1) . Clearing this bit to 0 disables the data ready interrupt from generating .
Bit 1: EP0-OUT Data Available Interrupt Enable (OUT0DAVIE). Setting this bit to 1 causes an interrupt to the CPU when
the EP0-OUT data is available (OUT0DAV = 1) . Clearing this bit to 0 disables the data ready interrupt from generating .
Register Name EPIEN
Register Description Endpoint Interrupt Enable Register
Register Address UADDR[4:0] = 06h
Bit # 7 6 5 4 3 2 1 0
Name — — SUDAVIE IN3BAVIE IN2BAVIE OUT1DAVIE OUT0DAVIE IN0BAVIE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw