Maxim Integrated MAXQ622 - Manual (Page 95)

MAXQ612/MAXQ622 User’s Guide
5-22 Maxim Integrated
REGISTER DESCRIPTION
SPICN1 (07h, 03h) SPI Control Register 1
Initialization: This buffer is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write except bit 7 is read-only .
SPICN1.0 (SPIEN) SPI Enable. Setting this bit to 1 enables the SPI module and its baud-rate generator for SPI
operation . Clearing this bit to 0 disables the SPI module and its baud-rate generator .
SPICN1.1 (MSTM) Master Mode Enable. MSTM functions as a master mode enable bit for the SPI module .
When MSTM is set to 1, the SPI operates as a master . When MSTM is cleared to 0, the
SPI module operates in slave mode . Note that this bit can be set from 0 to 1 only when the
SSEL signal is deasserted .
SPICN1.2 (MODFE) Mode Fault Enable. When set to 1 in master mode, this bit enables the use of SSEL input
as a mode fault signal; when cleared to 0, the SSEL has no function and its port pin can be
used for other purposes . In slave mode, the SSEL pin always functions as a slave select
input signal to the SPI module, independent of the setting of the MODFE bit .
SPICN1.3 (MODF) Mode Fault Flag. This bit is the mode fault flag when the SPI is operating as a master .
When mode fault detection is enabled as MODFE = 1 in master mode, a detection of a
high to low transition on the SSEL pin signifies a mode fault and sets the MODF to 1 . This
bit must be cleared to 0 by software once set . Setting this bit to 1 by software causes an
interrupt if enabled . This flag has no meaning in slave mode .
SPICN1.4 (WCOL) Write Collision Flag. This bit indicates a write collision when set to 1 . This is caused by
attempting to write to the SPIB while a transfer cycle is in progress . This bit must be cleared
to 0 by software once set . Setting this bit to 1 by software causes an interrupt if enabled .
SPICN1.5 (ROVR) Receive Overrun Flag. This bit indicates a receive overrun when set to 1 . This is caused
by two or more characters have been received since the last read by the processor . The
newer data is lost . This bit must be cleared to 0 by software once set . Setting this bit to 1 by
software causes an interrupt if enabled .
SPICN1.6 (SPIC) SPI Transfer Complete Flag. This bit indicates the completion of a transfer cycle when
set to 1 . This bit must be cleared to 0 by software once set . Setting this bit to 1 by software
causes an interrupt if enabled .
SPICN1.7 (STBY) SPI Transfer Busy Flag. This bit is used to indicate the current status of the SPI module .
STBY is set to 1 when starting a SPI transfer cycle and is cleared to 0 when the transfer
cycle is completed . This bit is controlled by hardware and is read-only for user software .
PR0 (08h, 03h) Phase Register 0
Initialization: The phase register is cleared to 0000h on all forms of reset .
Read/Write Access: Unrestricted read/write .
PR0.15 to PR0.0 Phase Register Bits 15:0. This register is used to load and read the 16-bit value in the
phase register that determines the baud rate for the serial port 0 .
SMD0 (09h, 03h) Serial Port Mode Register 0
Initialization: This register is cleared to 00h on all forms of reset .
Read/Write Access: Unrestricted read/write .
SMD0.0 (FEDE0) Framing Error-Detection Enable. This bit selects the function of SM0 (SCON0 .7):
FEDE = 0: SCON0 .7 functions as SM0 for serial port mode selection .
FEDE = 1: SCON0 .7 is converted to the framing error (FE) flag .
SMD0.1 (SMOD0) Serial Port 0 Baud-Rate Select. The SMOD selects the final baud rate for the
asynchronous mode:
SMOD = 1: 16 times the baud clock for mode 1 and 3,
32 times the system clock for mode 2 .
SMOD = 0: 64 times the baud clock for mode 1 and 3,
64 times the system clock for mode 2 .
SMD0.2 (ESI0) Enable Serial Port 0 Interrupt. Setting this bit to 1 enables interrupt requests generated by
the RI or TI flags in SCON0 . Clearing this bit to 0 disables the serial port interrupt .
SMD0.7 to SMD0.3 Reserved . Reads return 0 .