3 spi clock register (spickn), 4 spi data buffer register (spibn) – Maxim Integrated MAXQ622 User Manual
Page 155
MAXQ612/MAXQ622 User’s Guide
10-8
Maxim Integrated
10.8.3 SPI Clock Register (SPICKn)
Bits 7:0: Clock Divider Ratio Bits 7:0 (CKR[7:0]). This 8-bit value determines the system clock divide ratio to be
used for SPI master mode baud-clock generation . This register has no function when operating in slave mode as the
SPI clock generation circuitry is disabled . The frequency of the SPI master-mode baud rate is calculated using the
following equation:
SPI Baud Rate = (0 .5 x System Clock Frequency)/(CKR[7:0] + 1)
10.8.4 SPI Data Buffer Register (SPIBn)
Data for SPI is read from or written to this location . The serial transmit and receive buffers are separate, but both are
addressed at this location . Write access is allowed only outside the transfer cycle . When the STBY bit is set, write
attempts are blocked and cause a write collision error .
7
0
SPI Clock Register (SPICKn)
0
rw
0
rw
0
rw
0
rw
0
rw
0
rw
0
rw
0
rw
Power-On Reset and System Resets
Read (r), Write (w), or Special (s) access
15
0
SPI Data Buffer Register (SPIBn)
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
0
rs
Power-On Reset and System Resets
Read (r), Write (w), or Special (s) access