Maxim Integrated MAXQ622 - Manual (Page 168)

MAXQ612/MAXQ622 User’s Guide
Maxim Integrated 11-13
11.4.7 I 2 C Slave Address Register (I2CSLA)
Bit 7: Reserved. Reads returns zero.
Bits 6 to 0: I
2 C Slave Address Register (I2CSLA[6:0]). These address bits contain the address of the I 2 C device .
When a match to this address is detected, the I 2 C controller automatically acknowledges the transmitter with the
I2CACK bit value if the I 2 C module is enabled (I2CEN = 1) . The I2CAMI flag is set to 1 and the I2CMST bit is cleared
to 0 . An interrupt is generated to the CPU if enabled .
11.5 I 2 C Examples
11.5.1 I 2 C Example: Master Mode, Transmit
I 2 C configured as master, transmit to slave address 08h:
; Setup for Master Mode Transmit
move I2CCN, #003h
; I2CEN = 1, I2CMST = 1
call wait_busy ; Polling routine to wait for I2CBUSY to clear
move I2CCN, #043h ; I2CEN = 1, I2CMST = 1, I2CMODE = 0, I2CSTART = 1
call wait_start ; Polling routine to wait for I2CSTART to clear
call wait_busy ; Polling routine to wait for I2CBUSY to clear
move I2CIE.1, #01h ; Enable Transmit Complete Interrupt
move I2CBUF, #008h ; Slave address set to 08h
call wait_tx_complete ; Wait for transmit interrupt
;; Verify ACK from slave
move ACC, I2CST ; Move I2C Status Register to accumulator
and #080h
; Check for NACK bit set in status register
cmp #000h
jump ne, FAIL
; If NACK bit set, handle retransmission, else continue
move I2CBUF, #0aah ; Byte to transmit
call wait_tx_complete ; Wait for transmit interrupt
;; Verify ACK
Register Name I2CSLA
Register Description I 2 C Slave Address Register
Register Address M4[0Ah]
Bit # 7 6 5 4 3 2 1 0
Name — I2CSLA6 I2CSLA5 I2CSLA4 I2CSLA3 I2CSLA2 I2CSLA1 I2CSLA0
Reset 0 0 0 0 0 0 0 0
Access r rw rw rw rw rw rw rw