Rockwell Automation 1769-HSC Compact High Speed Counter Module - Manual (Page 93)

Rockwell Automation Publication 1769-UM006E-EN-P - July 2013 93
Module Configuration, Output, and Input Data Chapter 4
RCU - Reset Counter Underflow (Ctr n ResetCounterUnderflow)
A 0 to 1 transition of this bit causes the corresponding Ctr[
n]Underflow bit to be
reset.
D Inv - Direction Invert (Ctr n DirectionInvert)
This bit, when set, inverts the direction of the counter (
n) as follows:
• If the Ctr nDirectionInhibit bit is set when this bit is 0, the resulting
direction is up, increasing counts.
• If the Ctr nDirectionInhibit bit is set when this bit is 1, the resulting
direction is down, decreasing counts.
D Inh - Direction Inhibit (Ctr n DirectionInhibit)
This bit, when set, inhibits the direction of the input signal from being used by
the module.
Z Inv - Z Invert (Ctr n ZInvert)
When set, this bit inverts the Z
n value. The Zn value is also affected by the
Ctr
nZInhibit bit. If the CtrnZInhibit is set, the module uses CtrnZInvert for all
internal Z activities, preset, hold and store. Input state Z
n is not affected by this
bit.
Z Inh - Z Inhibit (Ctr n ZInhibit)
When set, this bit inhibits the Z
n state from being used by the module. However,
even if the counter is inhibited, it still will count the pulses at input. For example,
if the counter is inhibited with count of 10 and there are 10 more pulses after
which it was un-inhibited, then the current count instead of starting with 11 will
be 21 for the next pulse.
RREZ - Reset Rising Edge Z (Ctr n ResetRisingEdgeZ)
A 0 to 1 transition causes the Ctr[
n].RisingEdgeZ bit to be reset.
RPW - Reset Counter Preset Warning (Ctr n ResetCtrPresetWarning)
A 0 to 1 transition causes the Ctr[
n]PresetWarning bit to be reset.