Rockwell Automation 1769-HSC Compact High Speed Counter Module - Manual (Page 92)

92 Rockwell Automation Publication 1769-UM006E-EN-P - July 2013
Chapter 4 Module Configuration, Output, and Input Data
RBF - Reset Blown Fuse (ResetBlownFuse)
When the OvercurrentLatchOff bit is set and an overcurrent condition has
occurred, the real output remains off until this bit is cycled from 0 to 1(rising
edge).
Control Bits
The control bits for counter (
n) are described below.
En - Enable Counter (Ctr n En)
This bit, when set (1), enables the inputs to be counted. When reset (0), this bit
inhibits any activity of the A or B inputs from affecting the count, pulse interval,
and rate values.
SP - Soft Preset (Ctr n SoftPreset)
A 0 to 1 transition of this bit causes counter (
n) to be preset, changing the count
to the value in Ctr
nPreset.
RCO - Reset Counter Overflow (Ctr n ResetCounterOverflow)
A 0 to 1 transition of this bit causes the corresponding Ctr[
n]Overflow bit to be
reset.
Output Array Word 4 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reset Blown Fuse Not used RBF Not used
Output Array Words 5 to 8 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Counter 0 Control Bits (Word 5) Not used RPW RREZ Z Inh Z Inv D Inh D Inv RU RO SP En
Counter 1 Control Bits (Word 6) Not used RPW RREZ Z Inh Z Inv D Inh D Inv RU RO SP En
Counter 2 Control Bits (Word 7) Not used RPW Not used D Inv RU RO SP En
Counter 3 Control Bits (Word 8) Not used RPW Not used D Inv RU RO SP En
TIP The order of precedence for the Preset and Direct Write actions is as
follows:
1. Preset
2. Direct Write
IMPORTANT Setting any of the control bits under certain conditions of the
NumberOfCounters value will result in the input error flag,
Ctr[n].InvalidCounter. For more information, see IC - Invalid Counter
(Ctr[1].InvalidCounter to Ctr[3].Invalid Counter) table on
page 107 .