1 introduction, 1 designing a spdif input interface, 1 spdif clocking – Cirrus Logic CS4970x4 User Manual

Page 92: 2 designing an hdmi input interface, 1 hdmi clocking, 1 introduction -1, 1 designing a spdif input interface -1, 1 spdif clocking -1, 2 designing an hdmi input interface -1, 1 hdmi clocking -1

Introduction

CS4953x4/CS4970x4 System Designer’s Guide

DS810UM6

6-1

Chapter 6

System Design Requirements for SPDIF and

HDMI

™

Technology Interfaces

6.1 Introduction

This chapter describes system design requirements when designing SPDIF and HDMI

™

technologyinterfaces to the CS4953x4/CS4970x4 DSP.

6.1.1 Designing a SPDIF Input Interface

The default input source state of the CS4953x4/CS4970x4 DSP is SPDIF with Autodetect. This setting is
configurable in the flash_image.xml file should the user wish to use a different input source type.

6.1.1.1 SPDIF Clocking

Here are some clocking practices to follow when implementing SPDIF input to the CS4953x4/CS4970x4
DS:

•

The SPDIF input with respect to the CS4953x4/CS4970x4 DSP is DAI_DATA4 / DAI2_DATA0).

•

Glitch free clock transitions are required from the SPDIF receiver on stream changes For example,
when an input stream changes from 48KHz Dolby Digital to 96 KHz PCM and vice versa).

•

The recommended MCLK to LRCLK (Fs) ratio is 256*Fs.

•

Any noise on the clocks or incorrect value of the clocks could affect the audio output, even if the
SPDIF input is not currently in use by the CS4953x4/CS4970x4 DSP.

•

Ensure that DAI2 port clocks are active irrespective of the system input source.

•

If the HDMI Receiver SPDIF out is used as an input to the CS4953x4/CS4970x4 DSP, ensure that
the HDMI firmware (or additional hardware if required) provides the correct and stable clocks and
data is sent out to the CS4953x4/CS4970x4 DSP.

6.1.2 Designing an HDMI Input Interface

6.1.2.1 HDMI Clocking

Here are some clocking practices to follow when implementing HDMI input to the CS4953x4/CS4970x4
DS:

•

Set CS4953x4/CS4970x4 MCLK as a slave and mastered by the HDMI Rx. MCLK must stay at 24
MHz for all stream types (Legacy and HD).

•

In the event of an input stream change affecting the clocks, Cirrus Logic recommends holding the
CS4953x4/CS4970x4 DSP in Reset until the clocks are stable. For example, the Host Controller can
probe the HDMI Rx to determine when the clocks are stable.

This manual is related to the following products:

CS4953x4