Cirrus Logic CS4970x4 - Manual (Page 27)

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CS49
70x4 Pin Assign
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CS4953
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0x4 System Desig
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ide
106 - GPIO10 General Purpose Input/Output
1. PCP_A2
2. PCP_A10
3. SCP2_MOSI
1. Parallel Control Port Address Bit 2
2. Parallel Control Port Address Bit
10
3. SPI Mode Master Data Output/
Slave Data Input
3.3V (5V tol) BiDir IN
- 3 GPIO10 General Purpose Input/Output 1. SCP2_MOSI
1. SPI Mode Master Data Output/
Slave Data Input
3.3V (5V tol) BiDir IN
107 - GPIO40 General Purpose Input/Output
1. PCP_RD
2. PCP_R/W
1. Parallel Read Select (Intel Mode)
2. Parallel Read/Write Select
(Motorola and Multiplexed Mode)
3.3V (5V tol) BiDir IN
108 - GPIO41 General Purpose Input/Output
1. PCP_IRQ
2. SCP2_IRQ
1. Parallel Control Port Data Ready
Interrupt Request
2. Serial Control Port Data Ready
Interrupt Request
3.3V (5V tol) BiDir/OD IN
109 - GPIO9 General Purpose Input/Output
1. PCP_A1
2. PCP_A9 1. Parallel Control Port Address Bit 1
2. Parallel Control Port Address Bit 9
3.3V (5V tol) BiDir IN
- 4 GPIO9 General Purpose Input/Output 1. SCP1_IRQ
1. Serial Control Port Data Ready
Interrupt Request
3.3V (5V tol) BiDir IN
110 - GPIO8 General Purpose Input/Output
1. PCP_A0
2. PCP_A8 1. Parallel Control Port Address Bit 0
2. Parallel Control Port Address Bit 8
3.3V (5V tol) BiDir IN
- 5 GPIO8 General Purpose Input/Output 1. SCP2_IRQ
1. Serial Control Port Data Ready
Interrupt Request
3.3V (5V tol) BiDir IN
111 - GPIO7 General Purpose Input/Output
1. PCP_D7
2. PCP_AD7
1. Parallel Control Port Data Bus
2. Parallel Control Port Multiplexed
Address and Data Bus
3.3V (5V tol) BiDir IN
- 6 GPIO7 General Purpose Input/Output 1. SCP1_CS
2. IOWAIT
1. SPI Chip Select
2. SRAM Hold-Off Handshake
3.3V (5V tol) BiDir IN
112 - GPIO6 General Purpose Input/Output
1. PCP_D6
2. PCP_AD6
1. Parallel Control Port Data Bus
2. Parallel Control Port Multiplexed
Address and Data Bus
3.3V (5V tol) BiDir IN
- 7 GPIO6 General Purpose Input/Output
1. SCP2_CS
1. SPI Chip Select 3.3V (5V tol) BiDir IN
113 8 VDDIO7 I/O power supply voltage 3.3V PWR
114 - GPIO5 General Purpose Input/Output
1. PCP_D5
2. PCP_AD5
1. Parallel Control Port Data Bus
2. Parallel Control Port Multiplexed
Address and Data Bus
3.3V (5V tol) BiDir IN
115 - GPIO4 General Purpose Input/Output
1. PCP_D4
2. PCP_AD4
1. Parallel Control Port Data Bus
2. Parallel Control Port Multiplexed
Address and Data Bus
3.3V (5V tol) BiDir IN
116 9 GNDIO7 I/O ground 0V PWR
Table P-10. CS4970x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued)
LQFP-
144
Pin #
LQFP-
128
Pin #
Function 1
(Default)
Description of Default Function Secondary Functions Description of Secondary
Functions
Pwr Type
Reset
State