Table 1-2. supported spi flash read format -3 – Cirrus Logic CS4970x4 User Manual
Page 41
DS810
UM6
C
o
p
yrigh
t 201
3 Cirrus Log
ic, Inc
1
-3
Bo
oting the DSP
in
Ma
ste
r Boo
t Mode
CS4953
x4/CS497
0x4 System Desig
ner’s Gu
ide
Table 1-2. Supported SPI Flash Read Format
Pin 11 (144-Pin
Package)
Cycle Type Operation
Max
Freq.
(MHz)
1
1. SCP2_SCLK is 12.288 MHz (based on 24.576 MHz in CLKIN) during initial boot and then switches to 50 MHz once the PLL is locked.
Bus Cycle
2
2. One bus cycle is eight clock periods.
1
2
3
4
5
6
7
8
9
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
SCP2-
MOSI
SCP2-
MISO
High
50
0x03
Hi-Z
0x00
Hi-Z
0x00
Hi-Z
0x00
Hi-Z
X
3
3. x = Don’t care
D
OUT
(Byte 0)
X
D
OUT
(Byte 1)
X
D
OUT
(Byte 2)
X
D
OUT
(Byte 3)
X
D
OUT
(Byte 4)
Low
50
0x68
Hi-Z
0x00
Hi-Z
0x00
Hi-Z
0x00
Hi-Z
X
Hi-Z
X
Hi-Z
X
Hi-Z
X
Hi-Z
X
D
OUT