Cirrus Logic CS4970x4 - Manual (Page 90)

SDRAM Controller
CS4953x4/CS4970x4 System Designer’s Guide
DS810UM6 Copyright 2013 Cirrus Logic, Inc 5-5
DynamictAPR
Configure the last data out to active command time.
Bit 31:4 = 0 = Reserved
Bit 3:0 = Tapr, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF = 16 DSP clk cycles.
0x81000065
0xhhhhhhhh
Default 0x00000000
DynamictDAL
Configure the data-in to active command time.
Bit 31:4 = 0 = Reserved
Bit 3:0 = Tdal, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF = 16 DSP clk cycles.
Example:
Tdal = 6 CLKs (40 nS), HCLK = 150 MHz
Tdal = 6 -1 = 0x5
0x81000066
0xhhhhhhhh
Default 0x00000005
DynamictWR
Configure the write recovery time. Also known as Tdpl, Trwl
Bit 31:4 = 0 = Reserved
Bit 3:0 = Tdal, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF= 16 DSP clk cycles.
Example:
Twr = 2 CLKs (13.3 nS), HCLK = 150 MHz
Twr = 2 -1 = 0x1
0x81000067
0xhhhhhhhh
Default 0x00000001
DynamictRC
Configure the active to active command time.
Bit 31:5 = 0 = Reserved
Bit 4:0 = Trc, where:
0x0 to 0x1E = (n + 1) DSP clk cycles.
0x1F = 16 DSP clk cycles.
Example:
Trc = 65 nS, HCLK = 150 MHz
Trc = 65 nS * 150 MHz -1 =9.75 -1 = 0x9
0x81000068
0xhhhhhhhh
Default 0x00000007
DynamictRFC
Configure the auto refresh period and auto refresh to active command time. Also known as
Trrc
Bit 31:5 = 0 = Reserved
Bit 4:0 = Trc, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0x1F = 32 DSP clk cycles.
Example:
Trc = 65 nS, HCLK = 150 MHz
Trc = 65 nS * 150 MHz -1=9.75 -1 = 0x9
0x81000069
0xhhhhhhhh
Default 0x00000007
DynamictXSR
Configure the exit self refresh to active command time.
Bit 31:5 = 0 = Reserved
Bit 4:0 = Txsr, where:
0x0 to 0x1E = (n + 1) DSP clk cycles.
0x1F = 32DSP clk cycles.
Example:
Txsr = 83 nS, HCLK = 150 MHz
Txsr = 83 nS * 150 MHz-1 =12.45 -1 = 0xC
0x8100006A
0xhhhhhhhh
Default 0x00000009
Table 5-2. SDRAM Interface Parameters (Continued)
Mnemonic Hex Message