Cirrus Logic CS4970x4 - Manual (Page 22)

CS4970x4 Pin Assignments
CS4953x4/CS4970x4 System Designer’s Guide
DS810UM6 Copyright 2013 Cirrus Logic, Inc P-11
Configuration and control of the CS4953x4/CS4970x4x decoder and its peripherals are indirectly
executed through a messaging protocol supported by the operating system (OS) running on the DSP. In
other words, successful communication can only be accomplished by following the low-level hardware
communication format and high-level messaging protocol. The specifications of the messaging protocol
used by the OS can be found in AN288, “CS4953x4/CS4970x4 Firmware User’s Manual”. The system
designer only needs to read the subsection describing the communication mode being used. Other
chapters in this manual explain each communication mode in more detail.
P.6 CS4970x4 Pin Assignments
Table P-10 shows the pin assignments for both the 144- and 128-pin packages.
Table P-8. Reset Pin
LQFP-144
Pin #
LQFP-128
Pin #
Pin Name Pin Type Pin Description
93 121 RESET Input
Reset, async. active-low Chip Reset
Reset should be low at power-up to initialize the
DSP and to guarantee that the device is not
active during initial power-on stabilization
periods.
Table P-9. Hardware Strap Pins
LQFP-144
Pin #
LQFP-128
Pin #
Pin Name Pin Type Pin Description
7 39 DAO2_DATA1, HS4, GPIO19
Input
(at Reset)
Ouput
under
Normal
Operation
Operational Mode Select
Pull-up or Pull-down resistors on these pins set the DSP
operational mode at reset. Hardware Strap Mode Select
The state of these pins is latched at the rising edge of RESET.
The boot ROM uses the state of these pins to select the boot
mode.
11 43 DAO2_DATA0, HS3, GPIO18
16 48 DAO1_DATA2, HS2, GPIO16
17 49 DAO1_DATA1, HS1, GPIO15
19 51 DAO1_DATA0, HS0