Cirrus Logic CS4970x4 - Manual (Page 69)

Digital Audio Input Port Description
CS4953x4/CS4970x4 System Designer’s Guide
DS810UM6 Copyright 2013 Cirrus Logic, Inc 3-3
Figure 3-1. DAI Port Block Diagram
Currently supported are 4 lines of linear PCM input (DAI_DATA[3:0]) and 1 line of compressed audio or
linear PCM (DAI_DATA4). These two inputs can have their own clock domains. The firmware currently
available can operate on only one of these inputs at a time, providing for compressed data decode, stereo
PCM processing, or multichannel PCM processing. Please see AN288, “CS4953x4/CS4970x4 Firmware
User’s Manual” for details about configuring the firmware to select these different inputs to process.
3.2.3 BDI Port
Note:Currently not supported in the O/S.
The Bursty Data Input (BDI) port on the CS4953x4/CS4970x4 shares pins with the DAI port pins, and is
used for input of bursty compressed audio data. The compressed data is clocked in with a bit clock
(BDI_CLK). Bursty compressed audio data input requires the use of a “throttle” signal, BDI_REQ to signal
to the host that the CS4953x4/CS4970x4 is capable of accepting data.
3.2.4 Digital Audio Formats
The DAI has 5 stereo data input pins that are fully configurable including support for I
2
S, and left-justified
formats. DAI ports are programmed for Slave operation, where DAIn_LRCLK and DAIn_SCLK are inputs
only. This subsection describes some common audio formats that CS4953x4/CS4970x4 supports. It
should be noted that the input ports use up to 32-bit PCM resolution and 16-bit compressed data word
lengths.
3.2.4.1 I
2
S Format
For I
2
S, data is presented most-significant bit (MSB) first, one SCLK delay after the transition of
DAIn_LRCLK, and is valid on the rising edge of DAIn_SCLK. For the I
2
S format, the left subframe is
presented when DAIn_LRCLK is low, and the right subframe is presented when DAIn_LRCLK is high.
3.2.4.2 Left-Justified Format
Figure 3-2 illustrates the left-justified format with a rising-edge DAIn_SCLK. Data is presented most-
significant bit first on the first DAIn_SCLK after a DAIn_LRCLK transition and is valid on the rising edge of
DAIn_SCLK. For the left-justified format, the left subframe is presented when DAIn_LRCLK is high and
Table 3-2. Bursty Data Input (BDI) Pins
Pin Name Pin Description
LQFP-144
Pin #
LQFP-128
Pin #
Pin Type
BDI_REQ
Data Request, Active Low
BDI_REQ is the bursty delivery flow
control output for bursty audio data. It
indicates whether the DSP can accept
more data.
140 32 Output
BDI_CLK
Bit Clock 2 Bursty Audio Input Bit
Clock
BDI_CLK is the bit clock input for the
bursty serial audio data on BDI_DATA.
141 33 Input
BDI_DATA
Compressed Audio Bursty Input Data
BDI_DATA is the serial bursty audio
data input that corresponds to the
BDI_CLK serial bit clock..
142 34 Input