Cirrus Logic CS4970x4 - Manual (Page 83)

Digital Audio Output Port Description
CS4953x4/CS4970x4 System Designer’s Guide
DS810UM6 Copyright 2013 Cirrus Logic, Inc 4-9
Table 4-6 shows values and messages for the DAO_LRCLK polarity configuration parameter.
Table 4-7 shows values and messages for the DAO_SCLK polarity configuration parameter.
Table 4-8 shows values and messages for the output channel configuration parameter.
4.2.6 S/PDIF Transmitter
Two S/PDIF transmitters are provided on the XMTA and XMTB pins that can output an IEC60958-
compliant S/PDIF stream. The modulation clock source for the S/PDIF transmitter is the clock present on
the DAO_MCLK pin. The sample rate of the transmitter will be the same setting as for the respective DAO
port.
The DSP has an internal multiplexer that can be used to route an external S/PDIF signal from the
XMTA_IN or XMTB_IN pin directly to the respective XMTA/XMITB S/PDIF output pin instead of the
internally generated S/PDIF signal.
Table 4-6. Output DAO_LRCLK Polarity Configuration (Parameter E)
E Value DAO_LRCLK Polarity Hex Message
0 (default) LRCLK=Low indicates Left Subchannel
0x8140002C
0x00000700
0x8140002D
0x00000700
1 LRCLK=Low indicates Right Subchannel
0x8180002C
0xFFFFFBFF
0x8140002C
0x00000300
0x8180002D
0xFFFFFBFF
0x8180002D
0x00000300
Table 4-7. Output DAO_SCLK Polarity Configuration (Parameter F)
F Value DAO_SCLK Polarity Hex Message
0 (default) Data Valid on Rising Edge (clocked out on falling)
0x8180002C
0xFFFFEFFF
0x8180002D
0xFFFFEFFF
1 Data Valid on Falling Edge (clocked out on rising)
0x8140002C
0x00001000
0x8140002D
0x00001000
Table 4-8. Output Channel Configuration (Parameter G)
G Value Channel Configuration Hex Message
0
(default)
2 Channels
0x8180002C
0xFFFFF8FF
0x8140002C
0x00000700
1 6 Channels
0x8180002C
0xFFFFF8FF
0x8140002C
0x00000400