Cirrus Logic CS4970x4 User Manual
Page 37
DS810
UM6
C
op
yri
ght 2
013
Ci
rru
s
Lo
gic
P
-26
CS49
53x4 Pin Assign
me
nts
CS4953
x4/CS497
0x4 System Desig
ner’s Gu
ide
-
11
GPIO2
General Purpose Input/
Output
1. UART_TXD
1. UART Output
3.3V (5V
tol)
BiDir
IN
Y
119
12
VDD7
Core power supply voltage
1.8V
PWR
120
-
GPIO1
General Purpose Input/
Output
1. PCP_D1
2. PCP_AD1
1. Parallel Control Port Data Bus
2. Parallel Control Port Multiplexed
Address and Data Bus
3.3V (5V
tol)
BiDir
IN
Y
13
GPIO1
General Purpose Input/
Output
1. UART_RXD
1. UART Input
3.3V (5V
tol)
BiDir
IN
Y
121
-
GPIO0
General Purpose Input/
Output
1. PCP_D0
2. PCP_AD0
1. Parallel Control Port Data Bus
2. Parallel Control Port Multiplexed
Address and Data Bus
3.3V (5V
tol)
BiDir
IN
Y
14
GPIO0
General Purpose Input/
Output
1. UART_CLK
1. UART Clock
3.3V (5V
tol)
BiDir
IN
Y
122
15
GNDD7
Core ground
0V
PWR
123
16
XTAL_OUT
Buffered Reference Clock
Input/Crystal Oscillator Input
3.3V (5V
tol)
OUT
124
17
XTI
Reference Clock Input/
Crystal Oscillator Input
3.3V (5V
tol)
ANA
125
18
XTO
Crystal Oscillator Output 1
3.3V
ANA
126
19
GNDA
PLL ground
1.8V
PWR
127
-
NC
Do Not Connect on PCB
1.8V
ANA
128
20
PLL_REF_RES
Current Reference Output
for PLL. Connect to resistor.
3.3V
ANA
129
21
VDDA
PLL power.
3.3V
PWR
130
22
VDD8
Core power supply voltage
1.8V
PWR
131
23
GPIO14
General Purpose Input/
Output
1. DAI1_DATA3
2. DSD3
1. PCM Audio Input Data 3
2. DSD Audio Input Data 3
3.3V (5V
tol)
BiDir
IN
Y
132
24
GPIO13
General Purpose Input/
Output
1. DAI1_DATA2
2. DSD2
1. PCM Audio Input Data 2
2. DSD Audio Input Data 2
3.3V (5V
tol)
BiDir
IN
Y
133
25
GNDD8
Core ground
0V
PWR
134
26
GPIO12
General Purpose Input/
Output
1. DAI1_DATA1
2. DSD1
1. PCM Audio Input Data 1
2. DSD Audio Input Data 1
3.3V (5V
tol)
BiDir
IN
Y
135
27
DAI1_DATA0
PCM Audio Input Data 0
DSD0
DSD Audio Input Data 0
3.3V (5V
tol)
In
Y
136
28
VDDIO8
I/O power supply voltage
3.3V
PWR
137
29
DAI1_SCLK
PCM Audio Input Bit Clock
DSD_CLK
DSD Audio Input Clock
3.3V (5V
tol)
In
Y
Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued)
LQFP-
144
Pin #
LQFP-
128
Pin #
Function 1
(Default)
Description of Default
Function
Secondary Functions
Description of Secondary
Functions
Pwr
Type
Reset
State
Pullup
at
Reset