Cirrus Logic CS4970x4 User Manual
Page 34
DS810
UM6
C
op
yri
ght 2
013
Ci
rru
s
Lo
gic
P
-23
CS49
53x4 Pin Assign
me
nts
CS4953
x4/CS497
0x4 System Desig
ner’s Gu
ide
79
108
SD_CAS
SDRAM Column Address
Strobe
3.3V (5V
tol)
OUT
80
109
SD_RAS
SDRAM Row Address
Strobe
3.3V (5V
tol)
OUT
81
110
SD_CS
SDRAM Chip Select
3.3V (5V
tol)
OUT
82
111
EXT_A15
Flash Address Bit 15
3.3V (5V
tol)
OUT
83
112
VDD5
Core power supply voltage
1.8V
PWR
84
113
EXT_A16
Flash Address Bit 16
3.3V (5V
tol)
OUT
85
114
EXT_A17
Flash Address Bit 17
3.3V (5V
tol)
OUT
86
115
GNDD5
Core ground
0V
PWR
87
116
EXT_A18
Flash Address Bit 18
3.3V (5V
tol)
OUT
88
117
EXT_A19
Flash Address Bit 19
3.3V (5V
tol)
OUT
89
118
EXT_OE
Flash Output Enable
3.3V (5V
tol)
OUT
90
119
EXT_CS1
Active-low Flash chip select
3.3V (5V
tol)
OUT
91
120
VDDIO6
I/O power supply voltage
3.3V
PWR
92
-
GPIO30
General Purpose Input/
Output
1. CSW_U
2. XMTB_IN
1. Channel status user data input
2. S/PDIF Pass-thru Input
3.3V (5V
tol)
BiDir
IN
Y
93
121
RESET
Chip Reset
3.3V (5V
tol)
In
94
122
GNDIO6
I/O ground
0V
PWR
95
123
GPIO33
General Purpose Input/
Output
SCP1_MOSI
SPI Mode Master Data Output/Slave
Data Input
3.3V (5V
tol)
BiDir
IN
Y
96
-
GPIO32
General Purpose Input/
Output
1. SCP1_CS
2. IOWAIT
1. SPI Chip Select
2. SRAM Hold-Off Handshake
3.3V (5V
tol)
BiDir
IN
Y
97
124
GPIO34
General Purpose Input/
Output
1. SCP1_MISO
2. SCP1_SDA
1. SPI Mode Master Data Input/Slave
Data Output
2. I
2
C Mode Master/Slave Data IO
3.3V (5V
tol)
BiDir/OD
IN
Y
98
125
VDD6
Core power supply voltage
1.8V
PWR
Table P-11. CS4953x4 Pin Assignments (Continued) for 144-Pin and 128-Pin Packages (Continued)
LQFP-
144
Pin #
LQFP-
128
Pin #
Function 1
(Default)
Description of Default
Function
Secondary Functions
Description of Secondary
Functions
Pwr
Type
Reset
State
Pullup
at
Reset