2 operational mode selection, 3 booting the dsp in master boot mode, Table 1-1. operation modes -2 – Cirrus Logic CS4970x4 User Manual

Page 40: Table 1-1, "operation modes" on

1-2

DS810UM6

Operational Mode Selection
CS4953x4/CS4970x4 System Designer’s Guide

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1.2 Operational Mode Selection

The operational mode for the CS4953x4/CS4970x4 is selected by the values of the HS[4:0] pins on the
rising edge of RESET. This value determines the communication mode used until the part is reset again.
This value also determines the method for loading application code. The table below shows the different
operational modes and the HS[4:0] values for each mode.

1. In SPI Master mode 2, the following defaults are used: SPI Command Byte 0xE8, Image Start address 0x0 is sent as a 24-bit

value, 4 dummy bytes sent following the address (and before reading image data), SPI clock frequency = Fdclk / 2. This
mode supports the Atmel SPI Flash memory.

2. In SPI Master mode 3, the following defaults are used: SPI command byte 0x03, Image Start address 0x0 is sent as a 24-bit

value, no dummy bytes, SPI clock frequency = Fdclk / 2. This mode supports the ST SPI EEPROM devices.

3. For all SPI Master boot modes, by default Pin 25 (144-pin package) and Pin 14 (128-pin package) is used as EE_CS.

4. For Master boot modes, the following defaults are used: clock ratio=1:1, Endian Mode = Big Endian, Chip Select polarity =

active-low, 0-cycle delay from CS/Address Change to Output Enable, 4-cycle delay from CS to Read Access, SCP1- SPI
mode.

5. F

dclk

is specified in the CS4953xx and /CS4970x4 Data Sheets.

1.3 Booting the DSP in Master Boot Mode

When designing an AVR, the DSP must be connected as shown in

Figure 1-2

and

Figure 1-3

. Pay special

attention to the pull-up and pull-down resistors on each pin. These resistors are mode-select pins and
impact the behavior of the DSP after power-up. When the DSP is connected as shown in

Figure 1-2

and

Figure 1-3

, the DSP will boot from SPI Flash when Reset is released. The Read command word that is put

out on the address bus when Reset is released depends on the resistor on Pin 11.

Table 1-1

describes the

format of the Read command sent out by the DSP when Reset is released. The designer must select a
SPI Flash that supports the read format listed in

Table 1-1

. During internal development and testing, the

EON EN25P32, SST25VF, and the ST M25P80 SPI Flash devices were used for testing. If the SPI Flash
does not support the Read command listed in

Table 1-1