AMD SB600 - Manual (Page 187)

©2008 Advanced Micro Devices, Inc. IDE Controller (Device 20, Function 1)
AMD SB600 Register Reference Manual Proprietary Page 187
Device ID - R - 16 bits - [PCI_Reg:02h]
Field Name Bits Default Description
Device ID Register: This register holds a unique 16-bit value assigned to a device, and combined with the vendor ID
it identifies any PCI device.
Command - RW - 16 bits - [PCI_Reg:04h]
Field Name Bits Default Description
I/O Access Enable 0 0b I/O Access Enable. This bit controls access to the I/O space
registers. When this bit is 1, it enables access to Legacy IDE
ports, and PCI bus master IDE I/O registers are enabled.
Memory Access Enable 1 0b Memory Access Enable. This function is not implemented.
This bit is always 0.
Bus Master Enable 2 0b Master Enable. Bus master function enable.
1 = Enable
0 = Disable.
Special Cycle
Recognition Enable 3 0b Special Cycle recognition enable. This feature is not
implemented and this bit is always 0.
Memory Write and
Invalidate Enable 4 0b Memory Write and Invalidate Enable.
VGA Palette Snoop
Enable 5 0b VGA Palette Snoop Enable- The IDE host controller does not
need to snoop VGA palette cycles. This bit is always 0.
PERR- Detection Enable 6 0b PERR- (Response) Detection Enable bit - If set to 1, the IDE
host controller asserts PERR- when it is the agent receiving
data AND it detects a parity error. PERR- is not asserted if
this bit is 0.
Default - 0.
Wait Cycle Enable 7 0b Wait Cycle enable - The IDE host controller does not need to
insert a wait state between the address and data on the AD
lines. This bit is always 0.
SERR- Enable 8 0b SERR- enable - If set to 1, the IDE host controller asserts
SERR- when it detects an address parity error. SERR- is not
asserted if this bit is 0.
Default - 0.
Fast Back-to-Back
Enable 9 0b Fast Back-to-back enable. The IDE host controller only acts as
a master to a single device, so this functionality is not needed.
This bit is always 0.
Interrupt Disable 10 0b Interrupt disable bit (comply to PCI 2.3 spec.)
Reserved 15:11 00h Reserved. Always wired as 0’s.
Command Register: The PCI specification defines this register to control a PCI device’s ability to generate and
respond to PCI cycles.
Status - RW - 16 bits - [PCI_Reg:06h]
Field Name Bits Default Description
Reserved 2:0 0b Reserved. These bits are always read as 0.
Interrupt Status 3 0b Interrupt status bit. It complies with the PCI 2.3 specification.
Capabilities List 4 0b This bit is enabled by PCI Config offset 0x62 bit 13 to indicate
that the Capabilities Pointer is located at 34h.
66MHz Support 5 1b 66MHz capable. This feature is supported in the IDE host
controller.
UDF Supported 6 0b UDF Supported. This feature is not implemented and this bit is
always 0.
Fast Back-to-Back
Capable 7 0b Fast Back-to-Back Capable. This feature is not implemented
and this bit is always 0.
Data Parity Error 8 0b Data Parity reported – Set to 1 if the IDE host controller
detects PERR- asserted while acting as PCI master (whether
PERR- was driven by IDE host controller or not.)