AMD SB600 - Manual (Page 13)

©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 13
2 Register Descriptions: PCI Devices
2.1 SATA Registers (Device 18, Function 0)
Note: Some SATA functions are controlled by, and associated with, certain PCI configuration registers in the
SMBus/ACPI device. For more information refer to
section 2.3: SMBus Module and ACPI Block (Device 20,
Function 0) . The diagram below lists these SATA functions and the associated registers.
SATA
SATA Enables
SATA power saving
SATA Interrupt Map register
SATA Smart Power Control
AC/AFh 5Ch 98h
PCI_Reg:
2.1.1 PCI Configuration Space
The PCI Configuration Space registers define the operation of the SB600’s SATA controller on the PCI bus.
These registers are accessible only when the SATA controller detects a Configuration Read or Write
operation, with its IDSEL asserted, on the 32-bit PCI bus.
Register Name Offset Address
Vendor ID 00h
Device ID 02h
Command 04h
Status 06h
Revision ID/Class Code 08h
Cache Link Size 0Ch
Master Latency Timer 0Dh
Header Type 0Eh
BIST Mode Type 0Fh
Base Address 0 10h
Base Address 1 14h
Base Address 2 18h
Base Address 3 1Ch
Bus Master Interface Base Address 20h
AHCI Base Address 24h
Subsystem ID and Subsystem Vendor ID 2Ch
Capabilities Pointer 34h
Interrupt Line 3Ch
Interrupt Pin 3Dh
Min_gnt 3Eh
Max_latency 3Fh
Misc control 40h
Watch Dog Control And Status 44h
Watch Dog Counter 46h
MSI Control 50h
MSI Address 54h
MSI Upper Address 58h
MSI Data 5Ch
Power Management Capability ID 60h
Power Management Capability 62h
Power Management Control And Status 64h