AMD SB600 User Manual
Page 16
©2008 Advanced Micro Devices, Inc.
SATA Registers (Device 18, Function 0)
AMD SB600 Register Reference Manual
Proprietary
Page 16
Revision ID/Class Code- R - 32 bits - [PCI_Reg:08h]
Field Name
Bits
Default
Description
Note: This field is only writeable when PCI_Reg:40h[0] is set.
Sub-Class Code Program Interface Controller Type
01 8F IDE
06 01 AHCI
04 00 RAID
Cache Line Size - RW - 8 bits - [PCI_Reg:0Ch]
Field Name
Bits
Default
Description
Reserved 3:0
Reserved.
Cache Line Size Register
7:4
0h
If the value is 1, then the cache line size is 16 DW (64 byte).
Master Latency Timer - RW - 8 bits - [PCI_Reg:0Dh]
Field Name
Bits
Default
Description
Reserved 2:0
Reserved.
Master Latency Timer
7:3
00h
Master Latency Timer. This number, in units of clocks,
represents the guaranteed time slice allowed to the IDE host
controller for burst transactions.
Header Type - R - 8 bits - [PCI_Reg:0Eh]
Field Name
Bits
Default
Description
Header Type
7:0
00h
Header Type. Since the IDE host controller is a single-function
device, this register contains a value of 00h.
BIST Mode Type - RW - 8 bits - [PCI_Reg:0Fh]
Field Name
Bits
Default
Description
Completion Code
3:0
0h
Read Only.
Indicates the completion code status of BIST. A non-zero
value indicates a failure.
Reserved 5:4
Reserved.
Start BIST
6
0b
Since bit [7] is 0, program this bit take no effect.
BIST Capable
7
0b
Read Only. Hard-wired to ‘0’ indicating that there is no HBA
related BIST function.
Base Address 0 - RW - 32 bits - [PCI_Reg:10h]
Field Name
Bits
Default
Description
Resource Type Indicator
0
1b
RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
Reserved 2:1
Reserved.
Primary IDE CS0 Base
Address
31:3 0000_
0000h
Base Address for Primary IDE Bus CS0. This register is used
for native mode only. Base Address 0 is not used in
compatibility mode.
Base Address 1 - RW - 32 bits - [PCI_Reg:14h]
Field Name
Bits
Default
Description
Resource Type Indicator
0
1b
RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
Reserved 1
Reserved.
Primary IDE CS1 Base
Address
31:2 0000_
0000h
Base Address for Primary IDE Bus CS1. This register is used
for native mode only. Base Address 1 is not used in
compatibility mode.