Texas Instruments MSP430x4xx - Manual (Page 511)

Scan IF Registers
24-51 Scan IF
SIFCLKON Bit 5 High-frequency clock on. Setting this bit turns the high-frequency clock source
on for this state when SIFACLK = 1, even though the high frequency clock is
not used for the TSM. When the high-frequency clock is sourced from the
DCO, the DCO is forced on for this state, regardless of the MSP430 low-power
mode.
0
High-frequency clock is off for this state when SIFACLK = 1
1 High-frequency clock is on for this state when SIFACLK = 1
SIFCA Bit 4 TSM comparator on. Setting this bit turns the comparator on for this state
when SIFCAON = 0.
0
Comparator off during this state
1 Comparator on during this state
SIFEX Bit 3 Excitation and sample-and-hold. This bit, together with the SIFSH and
SIFTEN bits, enables the excitation transistor or samples the input voltage
during this state. SIFLCEN must be set to 1 when SIFEX = 1.
0
Excitation transistor disabled when SIFSH = 0 and SIFTEN = 1.
Sampling disabled when SIFSH = 1 and SIFTEN = 0.
1 Excitation transistor enabled when SIFSH = 0 and SIFTEN = 1.
Sampling enabled when SIFSH = 1 and SIFTEN = 0.
SIFLCEN Bit 2 LC enable. Setting this bit turns the damping transistor off, enabling the LC
oscillations during this state when SIFTEN = 1.
0
All SIFCHx channels are internally damped. No LC oscillations.
1 The selected SIFCHx channel is not internally damped. The LC
oscillates.
SIFCHx Bits
1-0 Input channel select. These bits select the input channel to be measured or
excited during this state.
00
SIFCH0
01 SIFCH1
10 SIFCH2
11 SIFCH3