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Serial clock polarity and phase, Figure 15−9. usart spi timing – Texas Instruments MSP430x4xx User Manual

Page 296

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USART Operation: SPI Mode

15-10

USART Peripheral Interface, SPI Mode

Serial Clock Polarity and Phase

The polarity and phase of UCLK are independently configured via the CKPL
and CKPH control bits of the USART. Timing for each case is shown in
Figure 15−9.

Figure 15−9. USART SPI Timing

CKPH CKPL

Cycle#

UCLK

UCLK

UCLK

UCLK

SIMO/

SOMI

SIMO/

SOMI

Move to UxTXBUF

RX Sample Points

0

1

0

0

0

1

1

1

0

X

1

X

MSB

MSB

1

2

3

4

5

6

7

8

LSB

LSB

TX Data Shifted Out

STE

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