Ifg1, interrupt flag register 1, Ifg2, interrupt flag register 2 – Texas Instruments MSP430x4xx User Manual
Page 286
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USART Registers: UART Mode
14-29
USART Peripheral Interface, UART Mode
IFG1, Interrupt Flag Register 1
7
6
5
4
3
2
1
0
UTXIFG0
URXIFG0
rw−1
rw−0
UTXIFG0
†
Bit 7
USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty.
0
No interrupt pending
1
Interrupt pending
URXIFG0
†
Bit 6
USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received
a complete character.
0
No interrupt pending
1
Interrupt pending
Bits
5-0
These bits may be used by other modules. See device-specific datasheet.
IFG2, Interrupt Flag Register 2
7
6
5
4
3
2
1
0
UTXIFG1
URXIFG1
rw−1
rw−0
Bits
7-6
These bits may be used by other modules. See device-specific datasheet.
UTXIFG1
Bit 5
USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF empty.
0
No interrupt pending
1
Interrupt pending
URXIFG1
Bit 4
USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received
a complete character.
0
No interrupt pending
1
Interrupt pending
Bits
3-0
These bits may be used by other modules. See device-specific datasheet.