Texas Instruments MSP430x4xx - Manual (Page 256)

Timer_B Registers
13-24 Timer_B
CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of
the corresponding CCIFG flag.
0
Interrupt disabled
1 Interrupt enabled
CCI Bit 3 Capture/compare input. The selected input signal can be read by this bit.
OUT Bit 2 Output. For output mode 0, this bit directly controls the state of the output.
0
Output low
1 Output high
COV Bit 1 Capture overflow. This bit indicates a capture overflow occurred. COV must
be reset with software.
0
No capture overflow occurred
1 Capture overflow occurred
CCIFG Bit 0 Capture/compare interrupt flag
0
No interrupt pending
1 Interrupt pending