Texas Instruments MSP430x4xx - Manual (Page 501)

Scan IF Registers
24-41 Scan IF
SIFIFG0 Bit 2 SIF interrupt flag 0. This bit is set by the SIFxOUT conditions selected by the
SIFIFGSETx bits. SIFIFG0 must be reset with software.
0
No interrupt pending
1 Interrupt pending
SIFTESTD Bit 1 Test cycle insertion. Setting this bit inserts a test cycle between TSM cycles.
SIFTESTD is automatically reset at the end of the test cycle.
0
No test cycle inserted
1 Test cycle inserted between TSM cycles.
SIFEN Bit 0 Scan interface enable. Setting this bit enables the Scan IF.
0
Scan IF disabled
1 Scan IF enabled