IBM uPD78082 - Manual (Page 58)

35
CHAPTER 3 CPU ARCHITECTURE
RETI and RETB
Instruction
PSW
PC15-PC8 PC15-PC8
PC7-PC0 Register Pair Lower
SP SP + 2
SP
Register Pair Upper
RET Instruction POP rp Instruction
SP + 1
PC7-PC0
SP SP + 2
SP
SP + 1
SP + 2
SP
SP + 1
SP SP + 3
Interrupt and
BRK Instruction
PSW
PC15-PC8
PC15-PC8
PC7-PC0 Register Pair Lower
SP SP _ 2
SP _ 2
Register Pair Upper
CALL, CALLF, and
CALLT Instruction PUSH rp Instruction
SP _ 1
SP
SP SP _ 2
SP _ 2
SP _ 1
SP
PC7-PC0 SP _ 3
SP _ 2
SP _ 1
SP
SP SP _ 3
0 15
SP
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area (FE00H-FEFFH for the
µ
PD78081, FD80H-FEFFH for the
µ
PD78082, and FD00H-FEFFH for the
µ
PD78P083) can be set as the stack area.
Figure 3-9. Stack Pointer Configuration
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from
the stack memory.
Each stack operation saves/resets data as shown in Figures 3-10 and 3-11.
Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before
instruction execution.
Figure 3-10. Data to be Saved to Stack Memory
Figure 3-11. Data to be Reset from Stack Memory