IBM uPD78082 - Manual (Page 18)

– vii –
FIGURE (2/4)
Fig. No. Title Page
6-10 8-Bit Timer Mode Control Register Setting for External Event Counter Operation ............. 93
6-11 External Event Counter Operation Timings (with Rising Edge Specification) .................... 93
6-12 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation .............. 94
6-13 8-Bit Timer Mode Control Register Settings for PWM Output Operation ........................... 96
6-14 PWM Output Operation Timing (Active high setting) .......................................................... 97
6-15 PWM Output Operation Timings (CRn0 = 00H, active high setting) ................................... 97
6-16 PWM Output Operation Timings (CRn0 = FFH, active high setting) .................................. 98
6-17 PWM Output Operation Timings (CRn0 changing, active high setting) .............................. 99
6-18 8-Bit Timer Registers 5 and 6 Start Timing ......................................................................... 100
6-19 External Event Counter Operation Timing .......................................................................... 100
6-20 Timing after Compare Register Change during Timer Count Operation ............................ 101
7-1 Watchdog Timer Block Diagram ......................................................................................... 105
7-2 Timer Clock Select Register 2 Format ................................................................................ 107
7-3 Watchdog Timer Mode Register Format ............................................................................. 108
8-1 Remote Controlled Output Application Example ................................................................ 111
8-2 Clock Output Control Circuit Block Diagram ....................................................................... 112
8-3 Timer Clock Select Register 0 Format ................................................................................ 113
8-4 Port Mode Register 3 Format ............................................................................................. 114
9-1 Buzzer Output Control Circuit Block Diagram .................................................................... 115
9-2 Timer Clock Select Register 2 Format ................................................................................ 117
9-3 Port Mode Register 3 Format ............................................................................................. 118
10-1 A/D Converter Block Diagram ............................................................................................ 120
10-2 A/D Converter Mode Register Format ................................................................................ 123
10-3 A/D Converter Input Select Register Format ...................................................................... 124
10-4 External Interrupt Mode Register 1 Format ........................................................................ 125
10-5 A/D Converter Basic Operation .......................................................................................... 127
10-6 Relations between Analog Input Voltage and A/D Conversion Result ................................ 128
10-7 A/D Conversion by Hardware Start .................................................................................... 129
10-8 A/D Conversion by Software Start ...................................................................................... 130
10-9 Example of Method of Reducing Current Dissipation in Standby Mode ............................. 131
10-10 Analog Input Pin Disposition .............................................................................................. 132
10-11 A/D Conversion End Interrupt Request Generation ...........................................................
10-12 Handling of AVDD Pin ......................................................................................................... 133
11-1 Serial Interface Channel 2 Block Diagram ......................................................................... 137
11-2 Baud Rate Generator Block Diagram ................................................................................. 138
11-3 Serial Operating Mode Register 2 Format .......................................................................... 140
11-4 Asynchronous Serial Interface Mode Register Format ....................................................... 141
11-5 Asynchronous Serial Interface Status Register Format ..................................................... 143
11-6 Baud Rate Generator Control Register Format (1/2) ......................................................... 144