IBM uPD78082 User Manual
Page 161
138
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
TPS3 TPS2 TPS1 TPS0
Internal Bus
MDL3 MDL2 MDL1 MDL0
Baud Rate Generator
Control Register
4
TXE
CSIE2
5-Bit
Counter
Selector
Selector
Decoder
1/2
Selector
Transmit
Clock
1/2
Selector
Receive
Clock
Match
Match
MDL0-MDL3
5-Bit
Counter
RXE
Start Bit Detection
Selector
f
xx
-f
xx
/2
10
TPS0-TPS3
SCK
CSCK
ASCK/SCK2/P72
4
4
Start Bit
Sampling Clock
Figure 11-2. Baud Rate Generator Block Diagram
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