IBM uPD78082 - Manual (Page 21)

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TABLE (1/2)
Table. No. Title Page
1-1 Differences between the
µ
PD78081, 78082 and 78P083, the
µ
PD78081(A), 78082(A)
and 78P083(A), and the
µ
PD78081(A2) ............................................................................ 13
2-1 Type of Input/Output Circuit of Each Pin ............................................................................ 22
3-1 Vector Table ........................................................................................................................ 28
3-2 Special-Function Register List (1/2) .................................................................................. 38
3-2 Special-Function Register List (2/2) ................................................................................... 39
4-1 Port Functions .................................................................................................................... 54
4-2 Port Configuration .............................................................................................................. 55
4-3 Port Mode Register and Output Latch Settings when Using Dual-Fucntions ..................... 64
5-1 Clock Generator Configuration ........................................................................................... 69
5-2 Maximum Time Required for CPU Clock Switchover ......................................................... 77
6-1 Timer/Event Counter Types and Functions ........................................................................ 79
6-2 8-Bit Timer/Event Counters 5 and 6 Interval Times ............................................................ 80
6-3 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ................................... 81
6-4 8-Bit Timer/Event Counters 5 and 6 Configurations ........................................................... 82
6-5 8-Bit Timer/Event Counters 5 and 6 Interval Times ............................................................ 92
6-6 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ................................... 95
7-1 Watchdog Timer Overrun Detection Times ......................................................................... 103
7-2 Interval Times ..................................................................................................................... 104
7-3 Watchdog Timer Configuration ........................................................................................... 105
7-4 Watchdog Timer Overrun Detection Time .......................................................................... 109
7-5 Interval Timer Interval Time ................................................................................................ 110
8-1 Clock Output Control Circuit Configuration ........................................................................ 112
9-1 Buzzer Output Control Circuit Configuration ...................................................................... 115
10-1 A/D Converter Configuration .............................................................................................. 119
11-1 Serial Interface Channel 2 Configuration ........................................................................... 136
11-2 Serial Interface Channel 2 Operating Mode Settings ......................................................... 142
11-3 Relation between Main System Clock and Baud Rate ....................................................... 146
11-4 Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) 147
11-5 Relation between Main System Clock and Baud Rate ....................................................... 155
11-6 Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) 156
11-7 Receive Error Causes ........................................................................................................ 161