IBM uPD78082 - Manual (Page 19)

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FIGURE (3/4)
Fig. No. Title Page
11-6 Baud Rate Generator Control Register Format (2/2) ......................................................... 145
11-7 Asynchronous Serial Interface Transmit/Receive Data Format .......................................... 157
11-8 Asynchronous Serial Interface Transmission Completion Interrupt Request Timing .......... 159
11-9 Asynchronous Serial Interface Reception Completion Interrupt Request Timing ............... 160
11-10 Receive Error Timing .......................................................................................................... 161
11-11 State of the Receive Buffer Register (RXB) when Reception is Interrupted, and
Generation/Non Generation of an Interrupt Request (INTSR) ........................................... 162
11-12 3-Wire serial I/O Mode Timing ............................................................................................ 168
11-13 Circuit of Switching in Transfer Bit Order ........................................................................... 169
12-1 Basic Configuration of Interrupt Function (1/2) ................................................................... 173
12-1 Basic Configuration of Interrupt Function (2/2) ................................................................... 174
12-2 Interrupt Request Flag Register Format ............................................................................. 176
12-3 Interrupt Mask Flag Register Format .................................................................................. 177
12-4 Priority Specify Flag Register Format ................................................................................. 178
12-5 External Interrupt Mode Register 0 Format ........................................................................ 179
12-6 External Interrupt Mode Register 1 Format ........................................................................ 179
12-7 Program Status Word Configuration ................................................................................... 180
12-8 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment ............ 182
12-9 Non-Maskable Interrupt Request Acknowledge Timing ...................................................... 182
12-10 Non-Maskable Interrupt Request Acknowledge Operation ................................................ 183
12-11 Interrupt Request Acknowledge Processing Algorithm ....................................................... 185
12-12 Interrupt Request Acknowledge Timing (Minimum Time) ................................................... 186
12-13 Interrupt Request Acknowledge Timing (Maximum Time) .................................................. 186
12-14 Example of Multiple Interrupt (1/2) ..................................................................................... 189
12-14 Example of Multiple Interrupt (2/2) ..................................................................................... 190
12-15 Interrupt Request Hold ....................................................................................................... 192
13-1 Oscillation Stabilization Time Select Register Format ........................................................ 194
13-2 HALT Mode Clear upon Interrupt Generation ..................................................................... 196
13-3 HALT Mode Release by RESET Input ................................................................................ 197
13-4 STOP Mode Release by Interrupt Generation .................................................................... 199
13-5 Release by STOP Mode RESET Input ............................................................................... 200
14-1 Block Diagram of Reset Function ....................................................................................... 201
14-2 Timing of Reset Input by RESET Input ............................................................................... 202
14-3 Timing of Reset due to Watchdog Timer Overflow ............................................................. 202
14-4 Timing of Reset Input in STOP Mode by RESET Input ...................................................... 202
15-1 Memory Size Switching Register Format ........................................................................... 206
15-2 Page Program Mode Flowchart .......................................................................................... 209
15-3 Page Program Mode Timing ............................................................................................... 210
15-4 Byte Program Mode Flowchart ........................................................................................... 211
15-5 Byte Program Mode Timing ................................................................................................ 212