IBM uPD78082 - Manual (Page 207)

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CHAPTER 12 INTERRUPT FUNCTION
12.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt
mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE
flag set to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with
ISP flag reset to 0).
The waiting time from the point when a maskable interrupt request is generated until interrupt processing is
executed is as shown in Table 12-3.
Please refer to Figures 12-12 and 12-13 concerning interrupt request acknowledgement timing.
Table 12-3. Times from Maskable Interrupt Request Generation to Interrupt Service
Minimum Time Maximum Time Note
When
××
PR=0 7 clocks 32 clocks
When
××
PR=1 8 clocks 33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock : (f
CPU
: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority
with the priority specify flag is acknowledged first. Also, when the same priority is specified with the priority specify
flag, the interrupt request with the higher default priority is acknowledged first.
Any reserved interrupt requests are acknowledged when they become acknowledgeable.
Figure 12-11 shows interrupt request acknowledge algorithms.
If a maskable interrupt request is acknowledged, the contents are saved to the stack in the order of first, program
status word (PSW), then, program counter (PC), then the IE flag is reset (0) and the contents of the acknowledged
interrupt request priority specification flag are transferred to the ISP flag.
Further, the data in the vector table which has been determined with each interrupt request, are loaded into the
PC and branched.
Return from the interrupt is possible with the RETI instruction.
f CPU
1