IBM uPD78082 - Manual (Page 105)

82
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
6.2 8-Bit Timer/Event Counters 5 and 6 Configurations
The 8-bit timer/event counters 5 and 6 consist of the following hardware.
Table 6-4. 8-Bit Timer/Event Counters 5 and 6 Configurations
Item Configuration
Timer register 8 bits
×
2 (TM5, TM6)
Register Compare register: 8 bits
×
2 (CR50, CR60)
Timer output 2 (TO5, TO6)
Control register Timer clock select register 5 and 6 (TCL5, TCL6)
8-bit timer mode control register 5 and 6 (TMC5, TMC6)
Port mode register 10 (PM10)
Figure 6-1. 8-Bit Timer/Event Counters 5 and 6 Block Diagram
Note Refer to Figures 6-2 for details of configurations of 8-bit timer/event counters 5 and 6 output control circuits.
Remark n = 5, 6
TCEn LVSn LVRn
TMC
n6
TMC
n1
TOEn
TCL
n3
TCL
n2
TCL
n1
TCL
n0
8-Bit Compare Register
(CRn0)
8-Bit Timer Register n
(TMn)
Internal Bus
Internal Bus
Match
OVF
Clear
Note
Selector
Selector
2
4
6
Output Control
Circuit
TO5/P100/TI5,
TO6/P101/TI6
TI5/P100/TO5,
TI6/P101/TO6
INTTMn
8-Bit Timer Mode
Control Register n
Timer Clock
Select Register n
2f
xx
-f
xx
/2 9
f xx /2 11