IBM uPD78082 - Manual (Page 48)

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CHAPTER 3 CPU ARCHITECTURE
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Spaces
Figures 3-1 to 3-3 shows memory maps.
Figure 3-1. Memory Map (
µ
PD78081)
Data memory
space
General Registers
32 × 8 bits
Internal ROM
8192
×
8 bits
CALLF Entry Area
CALLT Table Area
Vector Table Area
Program Area
Program Area
Unusable
Program
memory
space
Internal High-speed RAM
256 × 8 bits
Special Function
Registers (SFRs)
256
×
8 bits
F F 0 0 H
FEFFH
FEE0H
FEDFH
F E 0 0 H
FDFFH
2 0 0 0 H
1 F F F H
0 0 0 0 H
1 F F F H
0 0 0 0 H
1 0 0 0 H
0 F F F H
0 8 0 0 H
0 7 F F H
0 0 8 0 H
0 0 7 F H
0 0 4 0 H
0 0 3 F H
FFFFH