Echelon FT 3150 Smart Transceiver - Manual (Page 60)

Chapter 3 - Input/Output Interfaces
54 FT 3120 / FT 3150 Smart Transceiver Data Book
Notes:
1. The slave B write cycle (master read) CS pulse width is directly related to the slave B write data valid parameter and master read setup parame-
ter. To calculate the write cycle CS duration needed for a special application use:
t
sbcspw
= t
sbwdv
+ master’s read data setup before rising edge of CS
Refer to the master’s specification data book for the master read setup parameter. The slave read cycle minimum CS pulse width = 50 ns.
2. Refer to the FT 3120 and FT 3150 Smart Transceiver Datasheet for detailed measurement information.
3. The data hold parameter, t
sbwdh
, is measured to the disable levels shown in the FT 3120 and FT 3150 Smart Transceiver Datasheet, rather than
to the traditional data invalid levels.
4. In a slave B write cycle the timing parameters are the same for a control register (HS) write as for a data write.
5. Special applications: Both the state of CS and R/W determine a slave B write cycle. If CS can not be used for a data transfer, then toggling the R/
W line can be used with no changes to the hardware. In other words, if CS is held low during a slave B write cycle, a positive pulse (low to high
to low) on R/W can execute a data transfer. The low to high transition on R/W causes slave B to drive data with the same timing parameters as
t
sbwdv
(redefined R/W to write data valid). Likewise, the falling edge of R/W causes slave B to release the data bus with the same timing limits
as the CS rising edge in t
sbwdz
. This scenario is only true for a slave B write cycle and is not applicable to a slave B read cycle or any slave A
data transitions. This application may be helpful if the master has separate read and write signals but no CS signal. Caution must be taken to
ensure the bus is free before transfers to avoid bus contention.
Figure 3.20 Slave B Mode Timing
Data Transferring
The data transfer operation between the master and the slave is accomplished through the use of a virtual write token-
passing protocol. The write token is passed alternatively between the master and the slave on the bus in an infinite
ping-pong fashion. The owner of the token has the option of writing a series of data bytes, or alternatively, passing the
write token without any data. Figure 3.21 illustrates the sequence of operations for this token passing protocol.
Symbol Description Min Typ Max
t
sbrws
R/W setup before falling edge of CS
FT 3120 and FT 3150 Smart Transceivers 0 ns — —
t
sbrwh
R/W hold after rising edge of CS 0 ns — —
t
sbcspw
CS pulse width Note 1 — —
t
sbas
A0 setup to falling edge of CS 10 ns — —
t
sbah
A0 hold after rising edge of CS 0 ns — —
t
sbwdv
CS to write data valid — — 50 ns
t
sbwdh
Write data hold after rising edge of CS (Notes 2, 3) 0 ns 30 ns —
t
sbwdz
CS rising edge to Slave B release data bus (Note 2) — — 50 ns
t
sbrds
Read data setup before rising edge of CS 25 ns — —
t
sbrdh
Read data hold after rising edge of CS 10 ns — —
MASTER A0
SLAVE
DATA OUT
MASTER
DATA OUT
READ CYCLE
(MASTER WRITE)
WRITE CYCLE
(MASTER READ)
t
sbcspw
t
sbas
t
sbcspw
t
sbrdh
t
sbrds
t
sbwdz
t
sbwdh
t
sbwdv
t
sbrws
t
sbrws
t
sbah
t
sbrwh
LATCH
MASTER CS
MASTER R/W