Echelon FT 3150 Smart Transceiver - Manual (Page 57)

FT 3120 / FT 3150 Smart Transceiver Data Book 51
Parallel I/O Objects
/* This is the slave program. After reset, the output buffer is filled with data and
then the slave reads from the master. The slave then writes to the master. The slave’s
input buffer should contain [5,1,1,1,1,1]; the output buffer should contain
[7,1,2,3,4,5,6,7,0,0,0,0,0,0].
*/
IO_0 parallel slave parallel_bus;
#define MAX_IN 5
// maximum length of input data expected
#define OUT_LEN 7 // output length can be equal to or less than the
// max
#define MAX_OUT 13 // maximum array length
struct parallel_out // output structure
{
unsigned int len; // actual length of data to be output
unsigned int buffer[MAX_OUT]; // array setup for max length of data
// to be output
}p_out;
// output structure name
struct parallel_in
// input structure
{
unsigned int len; // actual length of buffer to be
// input
unsigned int buffer[MAX_IN]; // maximum input array
}p_in; // input structure name
unsigned int i;
when (reset)
{
p_out.len=OUT_LEN; // assign output length
for(i=0; i // fill output buffer with 1s
p_out.buffer[i]=i+1;
}
when (io_out_ready(parallel_bus))
{
io_out(parallel_bus, &p_out); // output buffer
}
when (io_in_ready(parallel_bus))
{
p_in.len=MAX_IN; // declare the maximum input buffer
// acceptable
io_in(parallel_bus, &p_in); // store input data in buffer
io_out_request(parallel_bus); // request to output buffer
} // end of program
Debugging the Above Programs: If a watchdog timeout occurs on either LonBuilder emulator, simultaneously reset
the two emulators using the reset pushbutton switches on the face of the emulators. Both JP1 and JP2 on the emulator
boards should be disconnected for this application.
Slave B Mode
The slave B mode is recommended for interfacing a FT Smart Transceiver acting as the slave to another
microprocessor acting as the master. When configured in slave B mode, the FT Smart Transceiver accepts IO8 as a
chip select and IO9 to specify whether the master will read or write, and accepts IO10 as a register select input. When
CS is asserted and either IO10 is low or IO10 is high and R/W is low, pins IO0 – IO7 form the bidirectional data bus.
When IO10 is high, R/W is high, and CS is asserted, IO0 is driven as the HS acknowledgment signal to the master.