GE Industrial Solutions Entellisys 5.0 Integrator's Guide - Manual (Page 24)

Entellisys Status Definitions 24
2
Table 2-6 Breaker status offsets
2.1.2 CPU FlexLogic Status
The following information is provided to determine the CPU’s role and the state of the external
control transfer feature.
The Active CPU Status uses one register. See System Operand States (1 item) on page 136 for
memory location.
Table 2-7 Active CPU Status bit field
Breaker Number Register
Offset Bit Offset Notes
Breaker 1 0 0
Breaker 2 0 13 Spans over two registers
Breaker 3 1 10 Spans over two registers
Breaker 4 2 7 Spans over two registers
... ... ... ...
Breaker 30 24 6 Spans over two registers
Bit Value Notes
0 CPU A CPU A is active
1 CPU B CPU B is active
2 CPU External Control Transfer 0=Active CPU determined by Entellisys
1=Active CPU determined by an external
device