Rainbow Electronics DS2154 - Manual (Page 9)

DS2154
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Receive Channel Clock [RCHCLK]. 256 KHz clock
which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic
store is disabled. Synchronous with RSYSCLK when
the receive side elastic store is enabled. Useful for par-
allel to serial conversion of channel data.
Receive Channel Block [RCHBLK]. A user program-
mable output that can be forced high or low during any of
the 32 E1 channels. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with
RSYSCLK when the receive side elastic store is
enabled. Useful for blocking clocks to a serial UART or
LAPD controller in applications where not all E1 chan-
nels are used such as Fractional E1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individ-
ual channels in drop–and–insert applications, for exter-
nal per–channel loopback, and for per–channel condi-
tioning. See Section 9 for details.
Receive Serial Data [RSER]. Received NRZ serial
data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive side elastic
store is enabled.
Receive Sync [RSYNC]. An extracted pulse, one
RCLK wide, is output at this pin which identifies either
frame or CAS/CRC multiframe boundaries. If the
receive side elastic store is enabled, then this pin can be
enabled to be an input at which a frame or multiframe
boundary pulse synchronous with RSYSCLK is applied.
Receive Frame Sync [RFSYNC]. An extracted 8 KHz
pulse, one RCLK wide, is output at this pin which identi-
fies frame boundaries.
Receive Multiframe Sync [RMSYNC]. Only used
when the receive side elastic store is enabled. An
extracted pulse, one RSYSCLK wide, is output at this
pin which identifies multiframe boundaries. If the
receive side elastic store is disabled, then this output will
output multiframe boundaries associated with RCLK.
Receive Data [RDATA]. Updated on the rising edge of
RCLK with the data out of the receive side framer.
Receive System Clock [RSYSCLK]. 1.544 MHz or
2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications
that do not use the elastic store. Can be burst at rates up
to 8.192 MHz.
Receive Signaling Output [RSIG]. Outputs signaling
bits in a PCM format. Updated on rising edges of RCLK
when the receive side elastic store is disabled. Updated
on the rising edges of RSYSCLK when the receive side
elastic store is enabled. See Section 13 for timing
examples.
Receive Loss of Sync / Loss of Transmit Clock
[RLOS/LOTC]. A dual function output that is controlled
by the TCR2.0 control bit. This pin can be programmed
to either toggle high when the synchronizer is searching
for the frame and multiframe or to toggle high if the TCLK
pin has not been toggled for 5
µ s.
Receive Carrier Loss [RCL]. Set high when the line
interface detects a loss of carrier. [Note: a test mode
exists to allow the DS2154 to detect carrier loss at
RPOSI and RNEGI in place of detection at RTIP and
RRING].
Receive Signaling Freeze [RSIGF]. Set high when the
signaling data is frozen via either automatic or manual
intervention. Used to alert downstream equipment of
the condition.
8 MHz Clock [8MCLK]. 8.192 MHz output clock that is
referenced to the clock that is output at the RCLK pin.
Receive Positive Data Output [RPOSO]. Updated on
the rising edge of RCLKO with the bipolar data out of the
line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output [RNEGO]. Updated
on the rising edge of RCLKO with the bipolar data out of
the line interface. This pin is normally tied to RNEGI.
Receive Clock Output [RCLKO]. Buffered recovered
clock from the E1 line. This pin is normally tied to
RCLKI.
Receive Positive Data Input [RPOSI]. Sampled on
the falling edge of RCLKI for data to be clocked through
the receive side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally con-
nected to RPOSO by tying the LIUC pin high.