Rainbow Electronics DS2154 - Manual (Page 65)

DS2154
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TRANSMIT SIDE AC TIMING Figure 14–7
t R t F
t CP
t CL t CH
t SU
t D2
t HD
t D2
t D2
t D2
t PW
t SU
t HD
t SU
TCLK
TSER/TSIG/
TDATA
TCHCLK
TCHBLK
TSYNC 1
TSYNC 2
TLCLK 5
TLINK
t D1
TESO
NOTES:
1. TSYNC is in the output mode (TCR1.0=1).
2. TSYNC is in the input mode (TCR1.0=0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during Sa–bit locations as defined in TCR2; no relationship between TLCLK/TLINK
and TSYNC is implied.