Rainbow Electronics DS2154 - Manual (Page 46)

DS2154
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Sa6 TSaCR.2 Additional Bit 6 Insertion Control Bit.
0=do not insert data from the TSa6 register into the transmit data stream
1=insert data from the TSa6 register into the transmit data stream
Sa7 TSaCR.1 Additional Bit 7 Insertion Control Bit.
0=do not insert data from the TSa7 register into the transmit data stream
1=insert data from the TSa7 register into the transmit data stream
Sa8 TSaCR.0 Additional Bit 8 Insertion Control Bit.
0=do not insert data from the TSa8 register into the transmit data stream
1=insert data from the TSa8 register into the transmit data stream
12.0 LINE INTERFACE FUNCTIONS
The line interface function in the DS2154 contains three
sections; (1) the receiver which handles clock and data
recovery, (2) the transmitter which waveshapes and drives the E1 line, and (3) the jitter attenuator. Each of
the these three sections is controlled by the Line Inter-
face Control Register (LICR) which is described below.
LICR: LINE INTERFACE CONTROL REGISTER (Address=18 Hex)
(MSB) (LSB)
L2 L1 L0 EGL JAS JABDS DJA TPD
SYMBOL POSITION NAME AND DESCRIPTION
L2 LICR.7 Line Build Out Bit 2. Transmit waveshape setting; see Table 12–2.
L1 LICR.6 Line Build Out Bit 1. Transmit waveshape setting; see Table 12–2.
L0 LICR.5 Line Build Out Bit 0. Transmit waveshape setting; see Table 12–2.
EGL LICR.4 Receive Equalizer Gain Limit.
0=–12 dB
1=–43 dB
JAS LICR.3 Jitter Attenuator Select.
0=place the jitter attenuator on the receive side
1=place the jitter attenuator on the transmit side
JABDS LICR.2 Jitter Attenuator Buffer Depth Select
0=128–bits
1=32–bits (use for delay sensitive applications)
DJA LICR.1 Disable Jitter Attenuator.
0=jitter attenuator enabled
1=jitter attenuator disabled
TPD LICR.0 Transmit Power Down.
0=normal transmitter operation
1=powers down the transmitter and 3–states the TTIP and TRING pins
12.1 RECEIVE CLOCK AND DATA
RECOVERY
The DS2154 contains a digital clock recovery system.
See the DS2154 Block Diagram in Section 1 and
Figure 12–1 for more details. The DS2154 couples to
the receive E1 shielded twisted pair or COAX via a 1:1
transformer. See Table 12–3 for transformer details.
The 2.048 MHz clock attached at the MCLK pin is inter-
nally multiplied by 16 via an internal PLL and fed to the
clock recovery system. The clock recovery system
uses the clock from the PLL circuit to form a 16 times
oversampler which is used to recover the clock and
data. This oversampling technique offers outstanding
jitter tolerance (see Figure 12–2).
Normally, the clock that is output at the RCLKO pin is the
recovered clock from the E1 AMI/HDB3 waveform pres-
ented at the RTIP and RRING inputs. When no AMI sig-
LICR